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1. 发明申请

US20090140338A1 METHOD OF FABRICATING PATTERNED SOI DEVICES AND THE RESULTING DEVICE STRUCTURES 失效
标题翻译：制作图案化SOI器件的方法和结果的器件结构
公开(公告)号：US20090140338A1
公开(公告)日：2009-06-04
申请号：US11949973
申请日：2007-12-04
申请人： Robert J. Gauthier, JR. , Rajendran Krishnasamy
发明人： Robert J. Gauthier, JR. , Rajendran Krishnasamy
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/26533 , H01L21/76243 , H01L21/76267 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/66575 , H01L29/66636 , H01L29/78
摘要： A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess.
摘要翻译：一种用于制造氧化硅（SOI）衬底上的集成电路的FET晶体管的方法和结果，包括以下步骤：在衬底上的栅极两侧的衬底中形成凹槽，将氧离子注入到凹槽中，并退火将氧离子转换成每个凹槽下方的SOI层的衬底。

2. 发明申请

US20090001413A1 METHOD OF DOPING FIELD-EFFECT-TRANSISTORS (FETs) WITH REDUCED STRESS/STRAIN RELAXATION AND RESULTING FET DEVICES 有权
标题翻译：具有减少的应力/应变松弛和结果FET器件的场效应晶体管（FET）的方法
公开(公告)号：US20090001413A1
公开(公告)日：2009-01-01
申请号：US11768266
申请日：2007-06-26
申请人： Robert J. Gauthier, JR. , Rajendran Krishnasamy
发明人： Robert J. Gauthier, JR. , Rajendran Krishnasamy
IPC分类号： H01L21/8238 , H01L29/778
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a FET transistor for an integrated circuit by the steps of forming recesses in a substrate on both sides of a gate on the substrate, halo/extension ion implanting into the recesses, and filling the recesses with embedded strained layers comprising dopants for in-situ doping of the source and drain of the transistor. The stress/strain relaxation of the resulting transistor is reduced.
摘要翻译：一种通过以下步骤制造用于集成电路的FET晶体管的方法：在基板的栅极的两侧的基板上形成凹槽，将卤素/延伸离子注入到凹部中，以及用包含掺杂剂的嵌入的应变层填充凹部，晶体管的源极和漏极的原位掺杂。所得晶体管的应力/应变松弛减小。

3. 发明申请

US20130258532A1 PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES 有权
公开(公告)号：US20130258532A1
公开(公告)日：2013-10-03
申请号：US13431347
申请日：2012-03-27
申请人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
发明人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H01L27/06 , H01L21/20 , H01L21/33 , G06F17/50 , H01L21/8249 , H01L29/06 , H01L29/73 , H02H7/20 , H01L21/331
CPC分类号： H01L27/0262 , G06F17/5072 , H01L21/8249 , H01L21/845 , H01L27/0255 , H01L27/06 , H01L27/1211 , H01L29/06
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

4. 发明申请

US20130009207A1 VERTICAL NPNP STRUCTURE IN A TRIPLE WELL CMOS PROCESS 有权
标题翻译：三维CMOS工艺中的垂直NPNP结构
公开(公告)号：US20130009207A1
公开(公告)日：2013-01-10
申请号：US13614072
申请日：2012-09-13
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/74
CPC分类号： H01L29/74 , H01L21/823892 , H01L27/0262 , H01L27/0928 , H01L2924/0002 , H01L2924/00
摘要： A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
摘要翻译：使用三阱CMOS工艺制造的垂直NPNP结构，以及制造垂直NPNP结构的方法，提供静电放电（ESD）保护的方法和BiCMOS集成电路的设计结构。垂直NPNP结构可用于从负电压ESD事件向输入/输出（I / O）焊盘提供片上保护。也可以使用垂直PNPN结构来保护相同的I / O焊盘免受正电压ESD事件的影响。

5. 发明申请

US20120300349A1 GATE DIELECTRIC BREAKDOWN PROTECTION DURING ESD EVENTS 有权
标题翻译：防静电事件期间门电绝缘保护
公开(公告)号：US20120300349A1
公开(公告)日：2012-11-29
申请号：US13115492
申请日：2011-05-25
申请人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
发明人： Michel J. Abou-Khalil , James P. Di Sarro , Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Yang Yang
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H02H9/046 , G06F17/5063 , H01L27/0285
摘要： Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor. Alternatively, the gate and source of an existing field-effect transistor are selectively coupled provide ESD isolation to the protected field-effect transistor.
摘要翻译：用于将场效应晶体管的栅极和栅极电介质与静电放电（ESD）隔离的保护电路，设计结构和方法。保护场效应晶体管位于受保护的场效应晶体管和电压轨之间。在正常工作条件下，保护场效应晶体管饱和，使受保护的场效应晶体管耦合到电压轨。保护场效应晶体管可以在芯片无电源时响应于ESD事件而被驱动成截止状态，这增加了受保护的场效应晶体管的栅极与电压轨之间的ESD电流路径的串联电阻。保护场效应晶体管两端的电压降可以降低受保护的场效应晶体管的栅极电介质上的ESD应力。或者，现有的场效应晶体管的栅极和源极被选择性地耦合到提供ESD隔离到受保护的场效应晶体管。

6. 发明申请

US20110185332A1 MODEL BASED SIMULATION AND OPTIMIZATION METHODOLOGY FOR DESIGN CHECKING 有权
标题翻译：基于模型的模拟和优化方法设计检查
公开(公告)号：US20110185332A1
公开(公告)日：2011-07-28
申请号：US12695494
申请日：2010-01-28
申请人： Robert J. Gauthier, JR. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
发明人： Robert J. Gauthier, JR. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.
摘要翻译：提供了一种用于模拟电路的方法，装置和程序产品。电路的多个元件由包括通过/不合格标准的器件模型表示。在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

7. 发明申请

US20100230732A1 FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC 有权
标题翻译：具有气隙介质的场效应晶体管
公开(公告)号：US20100230732A1
公开(公告)日：2010-09-16
申请号：US12547529
申请日：2009-08-26
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , WiIliam R. Tonti , Yun Shi
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , WiIliam R. Tonti , Yun Shi
IPC分类号： H01L29/772 , H01L21/336 , H01L21/30
CPC分类号： H01L29/66795 , H01L29/785
摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.
摘要翻译：一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。门通过气隙与身体的至少一部分分离。气隙也在第一平面。

8. 发明申请

US20100096536A1 ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING 有权
标题翻译：使用光电传感器的需求电路功能执行
公开(公告)号：US20100096536A1
公开(公告)日：2010-04-22
申请号：US12646292
申请日：2009-12-23
申请人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, JR. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , James W. Adkisson , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthier, JR. , Michael J. Hauser , Jed H. Rankin , William R. Tonti
IPC分类号： G01J1/44
CPC分类号： H01L23/5256 , H01L23/525 , H01L27/14609 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.
摘要翻译：公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。此外，为了将ESD保护装置与输入板断开，将封装的芯片放置在系统中。不需要额外的引脚。

9. 发明申请

US20090310267A1 METHOD, DESIGN STRUCTURES, AND SYSTEMS FOR CURRENT MODE LOGIC (CML) DIFFERENTIAL DRIVER ESD PROTECTION CIRCUITRY 失效
标题翻译：电流模式逻辑（CML）差分驱动器ESD保护电路的方法，设计结构和系统
公开(公告)号：US20090310267A1
公开(公告)日：2009-12-17
申请号：US12140485
申请日：2008-06-17
申请人： Robert J. Gauthier, JR. , Junjun Li , Ankit Srivastava
发明人： Robert J. Gauthier, JR. , Junjun Li , Ankit Srivastava
IPC分类号： H02H9/00
CPC分类号： H03F3/45188 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F2203/45466 , H03F2203/45486 , H03F2203/45504
摘要： A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.
摘要翻译：在机器可读数据存储介质上编码的硬件描述语言（HDL）设计结构，所述HDL设计包括在计算机辅助设计系统中处理时的元件，生成用于实现基于DRAM的高速缓存的动态刷新协议的设备的机器可执行表示。 HDL设计结构还包括具有差分驱动器的集成电路，包括：形成差分驱动器的第一驱动器和第二驱动器，驱动器并联耦合在第一电压源和第二电压源之间; 第一开关，其耦合到所述第一驱动器并且被配置为在ESD事件期间关闭所述第一驱动器，使得所述第一驱动器在所述ESD事件期间保持应力; 以及耦合到所述第二驱动器并被配置为在所述ESD事件期间关闭所述第二驱动器的第二开关，使得所述第二驱动器在所述ESD事件期间维持应力。

10. 发明申请

US20090302416A1 Programmable Electrical Fuse 有权
标题翻译：可编程电气保险丝
公开(公告)号：US20090302416A1
公开(公告)日：2009-12-10
申请号：US12135242
申请日：2008-06-09
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

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