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1. 发明授权

US06941528B2 Use of a layout-optimization tool to increase the yield and reliability of VLSI designs 失效
标题翻译：使用布局优化工具来提高VLSI设计的产出和可靠性
公开(公告)号：US06941528B2
公开(公告)日：2005-09-06
申请号：US10604962
申请日：2003-08-28
申请人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. The invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via.
摘要翻译：本发明提供了一种用于优化集成电路设计中的冗余通孔的布置的方法和结构。本发明首先通过确定哪些通孔没有冗余通孔来定位目标通孔。然后，本发明在目标通孔上或附近绘制标记物形状。标记形状仅在每个目标通孔的水平或垂直方向绘制。本发明同时将第一方向上的所有标记形状扩展到预定长度，或者直到标记形状达到接地规则的极限。在扩展期间，不同的标记形状将被扩展到不同的长度。本发明确定哪些标记形状被充分扩展以形成有效的冗余通路以产生第一组潜在的冗余通孔，并且本发明消除了不能充分扩展以形成有效的冗余通路的标记形状。

2. 发明授权

US07725864B2 Systematic yield in semiconductor manufacture 失效
标题翻译：半导体制造系统产量
公开(公告)号：US07725864B2
公开(公告)日：2010-05-25
申请号：US11854000
申请日：2007-09-12
申请人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

3. 发明授权

US07657859B2 Method for IC wiring yield optimization, including wire widening during and after routing 失效
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US07657859B2
公开(公告)日：2010-02-02
申请号：US11275076
申请日：2005-12-08
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

4. 发明授权

US07337415B2 Systematic yield in semiconductor manufacture 有权
标题翻译：半导体制造系统产量
公开(公告)号：US07337415B2
公开(公告)日：2008-02-26
申请号：US10711978
申请日：2004-10-18
申请人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H. Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, design changes are performed to make structures more likely to function, either by forming a more planar surface on the lower layer or by compensating in the upper layer for the lack of planarity. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，通过在下层上形成更平坦的表面或者通过在上层补偿缺乏平面性，进行设计变更以使结构更有可能起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

5. 发明申请

US20100023913A1 METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING 有权
标题翻译： IC接线优化方法，包括在路由和之后的线路宽带化
公开(公告)号：US20100023913A1
公开(公告)日：2010-01-28
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

6. 发明授权

US08230378B2 Method for IC wiring yield optimization, including wire widening during and after routing 有权
标题翻译： IC布线产量优化方法，包括布线期间和之后的线宽
公开(公告)号：US08230378B2
公开(公告)日：2012-07-24
申请号：US12572297
申请日：2009-10-02
申请人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
发明人： John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
摘要翻译：公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。该方法执行满足布线拥塞约束的初始全局路由。接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。使用关键区域产量模型进行布线后布线宽度和布线调整。此外，该方法允许优化已经路由的数据。

7. 发明授权

US07721240B2 Systematic yield in semiconductor manufacture 失效
标题翻译：半导体制造系统产量
公开(公告)号：US07721240B2
公开(公告)日：2010-05-18
申请号：US11966135
申请日：2007-12-28
申请人： Paul H Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Paul H Bergeron , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tendency to form a non-planar surface due to its design. Accordingly, structures built on a layer above the lower layer are formed on a more planar surface and thus are more likely to function properly. The changes to improve manufacturing yield are made at the design stage rather than at the fabrication stage.
摘要翻译：提供三维结构，其提高半导体器件中某些结构的制造成品率。三维结构考虑到上层和下层之间的相互作用，其中下层由于其设计而具有形成非平面表面的倾向。因此，构建在下层上方的层上的结构形成在更平坦的表面上，因此更有可能正常地起作用。提高制造产量的变化是在设计阶段而不是在制造阶段进行的。

8. 发明授权

US07062729B2 Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization 有权
标题翻译：在分层电路布局优化中从半整数解求解可行整数解的方法和系统
公开(公告)号：US07062729B2
公开(公告)日：2006-06-13
申请号：US10946677
申请日：2004-09-22
申请人： Michael S. Gray , Jason D. Hibbeler , Gustavo E. Tellez , Robert F. Walker
发明人： Michael S. Gray , Jason D. Hibbeler , Gustavo E. Tellez , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method (300) and system (500) for optimizing a circuit layout based on layout constraints (308) and objectives (312). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.
摘要翻译：一种用于基于布局约束（308）和目标（312）优化电路布局的方法（300）和系统（500）。该方法包括求解线性程序，以获得变量为整数或整数的理性解。解决方案为半整数的变量的严格约束和目标简化为2-SAT问题，进行分析以确定其可满足性。如果2-SAT问题不可满足，则删除一个或多个目标，以使2-SAT问题满足。线性程序的任何半整数结果根据满足2-SAT问题的真值赋值进行舍入。圆形的结果用于创建电路布局。

9. 发明授权

US06986109B2 Practical method for hierarchical-preserving layout optimization of integrated circuit layout 失效
标题翻译：集成电路布局分层维护布局优化的实用方法
公开(公告)号：US06986109B2
公开(公告)日：2006-01-10
申请号：US10438625
申请日：2003-05-15
申请人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
发明人： Robert J. Allen , Fook-Luen Heng , Alexey Y. Lvov , Kevin W. McCullen , Sriram Peri , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.
摘要翻译：本发明提供了一种修改分层集成电路布局的方法，其中使用这些变量的变量和公式表示分层布局元素的位置，这产生基于公式的分层布局。这些变量被约束为整数。本发明提供了一种用于通过与基于公式的分层布局相同的变量定义的目标函数来引导布局的修改的方法。本发明通过将常数替换为一些变量来简化基于公式的分层布局，使得每个公式被减少到涉及不超过两个剩余变量的表达式。这产生了简化的布局方程和简化的目标函数。这也产生了对由常量选择的值组成的分层布局修改的部分解决方案。

10. 发明授权

US06904575B2 Method for improving chip yields in the presence of via flaring 失效
标题翻译：在存在通孔燃烧的情况下提高芯片产量的方法
公开(公告)号：US06904575B2
公开(公告)日：2005-06-07
申请号：US10064098
申请日：2002-06-11
申请人： Robert J. Allen , Gustavo E. Tellez
发明人： Robert J. Allen , Gustavo E. Tellez
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： The current invention provides a modification procedure that reduces errors in integrated circuits due to via shorts while at the same time avoiding the unnesting of the layout design and thereby permitting verification of the layout design by LVS testing tools. The current invention identifies if potentially shorting vias have electrically redundant paths and, if so, creates cloned cells of the original cell but void of the potentially shorting vias. The cloned cell is electrically comparable to the original cell. In addition, each instantiation of the original cell in the shapes data base is replaced with the cloned cell when electrical redundancy is present. Also, the number of vias removed can be minimized or maximized while, at the same time, all via electrical shorts are removed, depending on the design requirements.
摘要翻译：本发明提供了一种修改过程，该过程减少了集成电路由于通路短路而产生的错误，同时避免了布局设计的不明显，从而允许LVS测试工具对布局设计的验证。本发明鉴定潜在短路通孔是否具有电冗余路径，如果是，则产生原始单元的克隆单元，但没有潜在的短路通孔。克隆的细胞与原始细胞电可比较。此外，当存在电冗余时，形状数据库中的原始单元的每个实例化被克隆单元替换。此外，取决于设计要求，可以将去除的通路的数量最小化或最大化，同时全部通过电气短路被去除。

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