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1. 发明授权

US08145176B2 Front end and high frequency receiver having quadrature low noise amplifier 有权
标题翻译：具有正交低噪声放大器的前端和高频接收器
公开(公告)号：US08145176B2
公开(公告)日：2012-03-27
申请号：US12800960
申请日：2010-05-26
申请人： Eise Carel Dijkmans , Dominicus Martinus Wilhelmus Leenaerts , Petrus Gerardus Maria Baltus
发明人： Eise Carel Dijkmans , Dominicus Martinus Wilhelmus Leenaerts , Petrus Gerardus Maria Baltus
IPC分类号： H04B1/26
CPC分类号： H03F3/45188 , H03F3/19 , H03F3/393 , H03F3/45242 , H03F2200/294 , H03F2200/331 , H03F2200/336 , H03F2200/372
摘要： A front end and a high frequency receiver (1) provided therewith are described, which front end comprises a quadrature low noise amplifier (2-1, 2-2) as a low noise amplifier. A high isolation between local oscillators (6-1, 6-2) and quadrature mixers (3-1, 3-2) is achieved thereby, reducing a DC offset at mixer outputs (7, 8). The quadrature low noise amplifier may be implemented as a differential class AB cascade arrangement of MOST or FET semiconductors (15). A low distortion receiver (1) having a high linearity is the result.
摘要翻译：描述了提供有前端和高频接收器（1）的前端包括作为低噪声放大器的正交低噪声放大器（2-1,2-2）。因此实现了本地振荡器（6-1,6-2）和正交混频器（3-1,3-2）之间的高隔离度，从而减小了混频器输出端的直流偏移（7,8）。正交低噪声放大器可以被实现为MOST或FET半导体的差分级AB级联布置（15）。结果是具有高线性度的低失真接收机（1）。

2. 发明授权

US06791423B2 Quadrature coupled controllable oscillator and communication arrangement 有权
标题翻译：正交耦合可控振荡器和通信布置
公开(公告)号：US06791423B2
公开(公告)日：2004-09-14
申请号：US10066348
申请日：2002-01-31
申请人： Dominicus Martinus Wilhelmus Leenaerts , Eise Carel Dijkmans
发明人： Dominicus Martinus Wilhelmus Leenaerts , Eise Carel Dijkmans
IPC分类号： H03K3281
CPC分类号： H03K3/354 , H03B5/1215 , H03B5/1221 , H03B5/1228 , H03B5/1243 , H03K3/0322
摘要： A quadrature coupled controlled oscillator comprising a first and a second circuit module, each of the circuit modules (100 and 100′) comprising an astable multivibrator circuit (103). The first circuit module is coupled with the second circuit module and the second circuit module is cross coupled with the first circuit module. Each of the circuit modules (100 and 100′) comprises a first and a second Voltage Controlled Current Source (101) (VCCS). In each of the circuit modules, each VCCS is coupled to a phase shifter (102) for shifting the phase of a current (110) supplied by the VCCS to a resonator (104) included in that circuit module. A communication arrangement (300) for communicating via a bi-directional communication channel (304), comprises an oscillator (303) as described above for generating a periodic signal. A receiving module (301) generates an output signal from the periodic signal and a receiving signal received from the channel (304). The arrangement further comprises an emission module (302) for generating an emission signal for emitting to the channel from the periodic signal and an input signal.
摘要翻译：一种正交耦合控制振荡器，包括第一和第二电路模块，每个电路模块（100和100'）包括不稳定的多谐振荡器电路（103）。第一电路模块与第二电路模块耦合，第二电路模块与第一电路模块交叉耦合。每个电路模块（100和100'）包括第一和第二压控电流源（101）（VCCS）。在每个电路模块中，每个VCCS耦合到移相器（102），用于将由VCCS提供的电流（110）的相位移位到包括在该电路模块中的谐振器（104）。用于经由双向通信信道（304）通信的通信装置（300）包括如上所述的用于生成周期性信号的振荡器（303）。接收模块（301）从周期信号和从信道（304）接收的接收信号产生输出信号。该装置还包括用于从周期信号和输入信号产生用于发射到信道的发射信号的发射模块（302）。

3. 发明授权

US06489814B2 Track and hold amplifier 有权
标题翻译：跟踪和保持放大器
公开(公告)号：US06489814B2
公开(公告)日：2002-12-03
申请号：US09817969
申请日：2001-03-27
申请人： Gian Hoogzaad , Eise Carel Dijkmans , Raf Lodewijk Jan Roovers
发明人： Gian Hoogzaad , Eise Carel Dijkmans , Raf Lodewijk Jan Roovers
IPC分类号： G11C2702
CPC分类号： G11C27/026
摘要： A track and hold amplifier for use in analog/digital-converters comprises, in succession, an input buffer, a pn-junction switch and hold a capacitor. A feedback is provided between the hold capacitor and the input buffer and a second pn-junction switch is provided to disable the feedback during the hold mode.
摘要翻译：用于模拟/数字转换器的轨道和保持放大器包括输入缓冲器，pn结开关和保持电容器。在保持电容器和输入缓冲器之间提供反馈，并且提供第二pn结开关以在保持模式期间禁止反馈。

4. 发明申请

US20100240336A1 Front end and high frequency receiver having quadrature low noise amplifier 有权
标题翻译：具有正交低噪声放大器的前端和高频接收器
公开(公告)号：US20100240336A1
公开(公告)日：2010-09-23
申请号：US12800960
申请日：2010-05-26
申请人： Eise Carel Dijkmans , Dominicus Martinus Wilhelmus Leenaerts , Petrus Gerardus Maria Baltus
发明人： Eise Carel Dijkmans , Dominicus Martinus Wilhelmus Leenaerts , Petrus Gerardus Maria Baltus
IPC分类号： H04B1/16
CPC分类号： H03F3/45188 , H03F3/19 , H03F3/393 , H03F3/45242 , H03F2200/294 , H03F2200/331 , H03F2200/336 , H03F2200/372
摘要： A front end and a high frequency receiver (1) provided therewith are described, which front end comprises a quadrature low noise amplifier (2-1, 2-2) as a low noise amplifier. A high isolation between local oscillators (6-1, 6-2) and quadrature mixers (3-1, 3-2) is achieved thereby, reducing a DC offset at mixer outputs (7, 8). The quadrature low noise amplifier may be implemented as a differential class AB cascade arrangement of MOST or FET semiconductors (15). A low distortion receiver (1) having a high linearity is the result.
摘要翻译：描述了提供有前端和高频接收器（1）的前端包括作为低噪声放大器的正交低噪声放大器（2-1,2-2）。因此实现了本地振荡器（6-1,6-2）和正交混频器（3-1,3-2）之间的高隔离度，从而减小了混频器输出端的直流偏移（7,8）。正交低噪声放大器可以被实现为MOST或FET半导体的差分级AB级联布置（15）。结果是具有高线性度的低失真接收机（1）。

5. 发明授权

US07489791B2 A/D converter with integrated biasing for a microphone 有权
标题翻译：具有麦克风集成偏置的A / D转换器
公开(公告)号：US07489791B2
公开(公告)日：2009-02-10
申请号：US09899449
申请日：2001-07-05
申请人： Henricus J. Kunnen, legal representative , Eise Carel Dijkmans
发明人： Eric Jurgen Van Der Zwan
IPC分类号： H04R3/00 , H03M1/06
CPC分类号： H04R3/00 , H03M3/356 , H03M3/43 , H03M3/456 , H04R19/016 , H04R25/00
摘要： A combination of a microphone and a sigma-delta A/D converter include at least one feedback loop, such as a DC feedback loop. The DC feedback loop provides the bias current for a junction FET of the microphone. In this way, the signal current from the FET can be injected directly into the input integrator of the sigma-delta A/D converter without the need of signal resistors in series with the FET.
摘要翻译：麦克风和Σ-ΔA/ D转换器的组合包括至少一个反馈回路，例如DC反馈回路。直流反馈回路为麦克风的结型FET提供偏置电流。以这种方式，来自FET的信号电流可以直接注入到Σ-ΔA / D转换器的输入积分器中，而不需要与FET串联的信号电阻。

6. 发明授权

US07113119B2 Electronic circuit with a sigma delta A/D converter 有权
标题翻译：具有Σ-ΔA/ D转换器的电子电路
公开(公告)号：US07113119B2
公开(公告)日：2006-09-26
申请号：US10502728
申请日：2002-12-23
申请人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems , Eise Carel Dijkmans
发明人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems , Eise Carel Dijkmans
IPC分类号： H03M3/00
CPC分类号： H03M3/348 , H03M3/424
摘要： The A/D convener has a digital output for outputting a digital output signal selected from a set of three or more available values. A feedback loop generates the digital output signal so that a time averaged difference between an analog input signal and an analog feedback signal representative of the digital output signal is minimized. A feedback signal generator generates successive signal levels of the feedback signal. A return to zero switch inserts predetermined return to zero levels between the signal levels in the feedback signal. The return to zero switch is also used to provide the signal level for one of the available values.
摘要翻译： A / D转换器具有用于输出从一组三个或更多个可用值中选择的数字输出信号的数字输出。反馈回路产生数字输出信号，使得模拟输入信号和表示数字输出信号的模拟反馈信号之间的时间平均差最小化。反馈信号发生器产生反馈信号的连续信号电平。返回到零开关将反馈信号中的信号电平之间的预定值恢复为零电平。返回零开关也用于为可用值之一提供信号电平。

7. 发明授权

US06646970B1 Thermomagnetic writing of pulse sequences of controlled magnitude and variably controlled duration 失效
标题翻译：具有受控幅度和可变控制持续时间的脉冲序列的热磁写入
公开(公告)号：US06646970B1
公开(公告)日：2003-11-11
申请号：US09708151
申请日：2000-11-08
申请人： Albert H. J. Immink , Eise Carel Dijkmans , James J. A. McCormack , Andre G. J. Slenter
发明人： Albert H. J. Immink , Eise Carel Dijkmans , James J. A. McCormack , Andre G. J. Slenter
IPC分类号： G11B700
CPC分类号： G11B7/126 , G11B7/0045 , G11B11/10506 , G11B20/10194 , G11B20/1426
摘要： A device according to the invention for writing information to an information carrier (1) includes conversion means (7) for converting symbols in an information signal (SINFO) into pulse sequences in a control signal (STR). The device further includes a transducer (10) for generating a physically detectable pattern on the information carrier (1) in response to the control signal (STR). The conversion means (7) include assignment means (702) for assigning properties of the pulse sequences to symbols in the information signal (SINFO). These properties include the duration and the magnitude of pulses in the pulse sequence. The conversion means (7) further include at least one counter (711) for supplying a count signal (TC1) after a time interval, which counter is coupled to the assignment means (702). The conversion means (7) further include a controllable delay line (761) coupled to the at least one counter (711), for delaying the count signal (TC1), and to the assignment means (702).
摘要翻译：根据本发明的用于将信息写入信息载体（1）的装置包括用于将信息信号（SINFO）中的符号转换为控制信号（STR）中的脉冲序列的转换装置（7）。该装置还包括用于响应于控制信号（STR）在信息载体（1）上产生物理可检测图案的换能器（10）。转换装置（7）包括用于将脉冲序列的属性分配给信息信号（SINFO）中的符号的分配装置（702）。这些属性包括脉冲序列中脉冲的持续时间和幅度。转换装置（7）还包括用于在时间间隔之后提供计数信号（TC1）的至少一个计数器（711），该计数器耦合到分配装置（702）。转换装置（7）还包括耦合到至少一个计数器（711）的可控延迟线（761），用于延迟计数信号（TC1）和分配装置（702）。

8. 发明授权

US06784753B2 Method for modulating an output voltage of a RF transmitter circuit, and RF transmitter circuit 有权
标题翻译：用于调制RF发射机电路的输出电压的方法和RF发射机电路
公开(公告)号：US06784753B2
公开(公告)日：2004-08-31
申请号：US10144528
申请日：2002-05-13
申请人： Dominicus Martinus Wilhelmus Leenaerts , Eise Carel Dijkmans
发明人： Dominicus Martinus Wilhelmus Leenaerts , Eise Carel Dijkmans
IPC分类号： H03B508
CPC分类号： H03C3/0966 , H03B5/1212 , H03B5/1221 , H03B5/1228 , H03B5/1253 , H03B5/1293 , H03B2201/0208 , H04B1/04
摘要： The invention relates to a method for modulating an output voltage of a transmitter circuit comprising a voltage controlled oscillator, a digital/analog converter and an antenna circuit, the method comprising the method comprising sending an output signal of sufficient power from the voltage controlled oscillator directly to the antenna circuit and directly modulating a frequency of the output signal of the voltage controlled oscillator. The invention furthermore relates to a transmitter circuit comprising a voltage controlled oscillator having a tank circuit, a digital/analog converter and an antenna circuit, wherein the voltage controlled oscillator is adapted to send an output signal of sufficient power directly to the antenna circuit and wherein the digital/analog converter is arranged to modulate an output frequency of the voltage controlled oscillator. A capacitive load circuit may be connected to the tank circuit or a crystal oscillator circuit of the voltage controlled oscillator for modulating the frequency of the voltage controlled oscillator.
摘要翻译：本发明涉及一种用于调制包括压控振荡器，数字/模拟转换器和天线电路的发射机电路的输出电压的方法，该方法包括直接从压控振荡器发送足够功率的输出信号到天线电路并直接调制压控振荡器的输出信号的频率。本发明还涉及一种包括具有振荡电路，数字/模拟转换器和天线电路的压控振荡器的发射机电路，其中压控振荡器适于将足够功率的输出信号直接发送到天线电路，其中数字/模拟转换器被布置成调制压控振荡器的输出频率。容性负载电路可以连接到用于调制压控振荡器的频率的压控振荡器的振荡电路或晶体振荡器电路。

9. 发明授权

US06501407B2 Digital to analog converter 失效
标题翻译：数模转换器
公开(公告)号：US06501407B2
公开(公告)日：2002-12-31
申请号：US09962652
申请日：2001-09-25
申请人： Jan Roelof Westra , Anne Johan Annema , Jeroen Michiel Van Den Boom , Eise Carel Dijkmans
发明人： Jan Roelof Westra , Anne Johan Annema , Jeroen Michiel Van Den Boom , Eise Carel Dijkmans
IPC分类号： H03M166
CPC分类号： H03M1/808
摘要： A digital to analog converter (DAC) for converting a digital signal (DS) having a maximum voltage range which corresponds to a first supply voltage (UL) into an analog signal (Uout) having a maximum voltage range which corresponds to a second supply voltage (UH). The first supply voltage (UL) is offered between a first supply terminal (VSS) and a second supply terminal (VDDL). The second supply voltage (UH) is offered between the first supply terminal (VSS) and a third supply terminal (VDDH). The digital to analog converter (DAC) comprises conversion resistors (RCNV0-RCNVn) and coupling means (CPL) for coupling a number of said conversion resistors (RCNV2-RCNVn) in between the first supply terminal (VSS) and an output terminal (OUT), and for coupling the remainder of said conversion resistors (RCNV0-RCNV1) in between the third supply terminal (VDDH) and the output terminal (OUT). The value of said number depends on the data content of the digital signal (DS). Digital to analog converters are generally implemented in ICs. For modern ICs there is a trend toward ever decreasing supply voltages. Often circuits implemented in new IC processes have to be able to interface with ICs processed in less modern processes which are generally operated on higher supply voltages. In the modern process, therefore, circuits designed in modern ICs have to cope with voltages which are above the maximum specification for their transistors or other components. The DA-converter (DAC) mentioned above fulfils this requirement by the fact that material, such as polycrystalline silicon, is used for the conversion resistors (RCNV2-RCNVn), which material can cope with relatively high voltages, and furthermore by the fact that only the coupling means (CPL) have to be designed to cope with relatively high voltages.
摘要翻译：一种用于将具有对应于第一电源电压（UL）的最大电压范围的数字信号（DS）转换为具有对应于第二电源电压的最大电压范围的模拟信号（Uout）的数模转换器（DAC）（UH）。在第一电源端子（VSS）和第二电源端子（VDDL）之间提供第一电源电压（UL）。在第一电源端子（VSS）和第三电源端子（VDDH）之间提供第二电源电压（UH）。数模转换器（DAC）包括转换电阻（RCNV0-RCNVn）和耦合装置（CPL），用于将第一电源端（VSS）和输出端（OUT）之间的多个所述转换电阻（RCNV2-RCNVn）），并且用于将第三电源端子（VDDH）和输出端子（OUT）之间的所述转换电阻器（RCNV0-RCNV1）中的其余部分耦合。所述数字的值取决于数字信号（DS）的数据内容。数字到模拟转换器通常在IC中实现。对于现代IC来说，电源电压不断下降的趋势。通常在新IC工艺中实现的电路必须能够与通常以更高电源电压工作的较不现代的工艺中处理的IC相连接。因此，在现代流程中，在现代IC中设计的电路必须处理高于其晶体管或其他部件的最大规格的电压。上述DA转换器（DAC）通过以下事实满足了这一要求：诸如多晶硅的材料用于转换电阻器（RCNV2-RCNVn），该材料可以处理相对高的电压，此外，由于只有耦合装置（CPL）必须被设计成能够处理相对较高的电压。

10. 发明授权

US07787847B2 Front end and high frequency receiver having quadrature low noise amplifier 有权
标题翻译：具有正交低噪声放大器的前端和高频接收器
公开(公告)号：US07787847B2
公开(公告)日：2010-08-31
申请号：US10055388
申请日：2002-01-23
申请人： Eise Carel Dijkmans , Dominicus Martinus Wilhelmus Leenaerts , Petrus Gerardus Maria Baltus
发明人： Eise Carel Dijkmans , Dominicus Martinus Wilhelmus Leenaerts , Petrus Gerardus Maria Baltus
IPC分类号： H04B1/06
CPC分类号： H03F3/45188 , H03F3/19 , H03F3/393 , H03F3/45242 , H03F2200/294 , H03F2200/331 , H03F2200/336 , H03F2200/372
摘要： A front end and a high frequency receiver provided therewith are described, which front end comprises a quadrature low noise amplifier as a low noise amplifier. A high isolation between local oscillators and quadrature mixers is achieved thereby, reducing a DC offset at mixer outputs. The quadrature low noise amplifier may be implemented as a differential class AB cascode arrangement of MOST or FET semiconductors. A low distortion receiver having a high linearity is the result.
摘要翻译：描述了前端和设置的高频接收机，其前端包括作为低噪声放大器的正交低噪声放大器。从而实现了本地振荡器和正交混频器之间的高隔离度，从而降低了混频器输出端的直流偏移。正交低噪声放大器可以被实现为MOST或FET半导体的差分级AB共源共栅排列。结果是具有高线性度的低失真接收机。

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