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1. 发明授权

US5329176A Self-timed clocking system and method for self-timed dynamic logic circuits 失效
标题翻译：自定时钟系统和自定时动态逻辑电路的方法
公开(公告)号：US5329176A
公开(公告)日：1994-07-12
申请号：US137902
申请日：1993-09-29
申请人： Robert H. Miller, Jr. , Jeffry D. Yetter , Glenn T. Colon-Bonet , Robert J. Martin
发明人： Robert H. Miller, Jr. , Jeffry D. Yetter , Glenn T. Colon-Bonet , Robert J. Martin
IPC分类号： G06F7/50 , G06F7/501 , H03K19/094 , H03K19/096 , H03K19/21 , H03K19/017
CPC分类号： G06F7/5016 , H03K19/094 , H03K19/0966 , H03K19/215
摘要： A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed logic evaluation on vector inputs to derive a vector output. An evaluation done detector monitors the output of the logic block and determines when the vector output is valid. An edge detector detects the rising and falling edges of an arbitrary periodic timing signal. Finally, a logic block clock generator is set by the edge detector and reset by the evaluation done detector so as to provide precharging signals to the logic block, thereby defining respective precharge periods, and to provide evaluation periods for the self-timed logic evaluations in the logic block. In a specific implementation, the speed of logic evaluations is twice the speed of the system clock.
摘要翻译：为具有级联自定时动态逻辑门的逻辑块提供时钟系统和方法。动态逻辑门并行预充电，并对矢量输入进行自定时逻辑评估，以得出矢量输出。评估完成检测器监视逻辑块的输出，并确定矢量输出何时有效。边缘检测器检测任意周期性定时信号的上升沿和下降沿。最后，由边缘检测器设置逻辑块时钟发生器并由评估完成检测器复位，以便向逻辑块提供预充电信号，从而定义相应的预充电周期，并且提供用于自适应逻辑评估的评估周期逻辑块。在具体实现中，逻辑评估的速度是系统时钟速度的两倍。

2. 发明授权

US5740181A Method and apparatus for at speed observability of pipelined circuits 失效
标题翻译：流水线回路速度可观测的方法和装置
公开(公告)号：US5740181A
公开(公告)日：1998-04-14
申请号：US662403
申请日：1996-06-12
申请人： Craig A. Heikes , Glenn T. Colon-Bonet , David R. Smentek , Robert H. Miller, Jr.
发明人： Craig A. Heikes , Glenn T. Colon-Bonet , David R. Smentek , Robert H. Miller, Jr.
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318522
摘要： The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.
摘要翻译：通过在连续的时钟周期内将两组或更多组数据发送到流水线来观察流水线的操作。时钟自由运行，因为它需要数据传播通过管道的阶段。只有当感兴趣的数据分别保存在每个输出锁存器中时，才会对流水线的每一级的输出锁存器进行采样。观察可以通过标准测试访问端口（TAP）完全控制。观察可以通过暂停时钟来扫描新数据并导出，或者与时钟自由运行来实现。管道的输入可能来自测试寄存器或来自在正常操作期间馈送流水线的电路。

3. 发明授权

US5424996A Dual transparent latch 失效
标题翻译：双透明闩锁
公开(公告)号：US5424996A
公开(公告)日：1995-06-13
申请号：US953158
申请日：1992-09-29
申请人： Robert J. Martin , Glenn T. Colon-Bonet , Brian C. Miller
发明人： Robert J. Martin , Glenn T. Colon-Bonet , Brian C. Miller
IPC分类号： G11C7/10 , G11C8/06 , H03K3/012 , H03K3/037 , G11C8/00 , G11C7/00
CPC分类号： H03K3/037 , G11C7/1078 , G11C8/06 , H03K3/012
摘要： A dual transparent latch circuit is disclosed comprising two latches cross coupled together by two control lines to enable the latches collectively to input and output data at twice the frequency of the master clock frequency which controls the timing of each latch individually. The control lines are controlled by a clock generator such that one latch is enabled to receive and store data while the other latch is enabled to output data stored therein. At the same time, the latch receiving and storing the data is disabled from providing an output of the stored data and the latch providing the output is disabled from receiving and storing the data. The clock generator switches the states of the control lines such that they enable or disable the input of data to and output of data from the latches on each phase of the master clock signal. A dual transparent latch with triple edge timing is also disclosed. A method for generating a master signal having a master frequency and selectively enabling inputs at an input data rate greater than the master frequency to input data into memory and selectively enabling outputs at the input data rate to output data from memory.
摘要翻译：公开了一种双透明锁存电路，其包括由两个控制线交叉耦合在一起的两个锁存器，以使得锁存器能够共同地以主控制器频率的频率的两倍输入和输出，该时钟频率分别控制每个锁存器的定时。控制线由时钟发生器控制，使得一个锁存器能够接收和存储数据，而另一个锁存器被使能以输出存储在其中的数据。同时，禁止接收和存储数据的锁存器提供存储的数据的输出，并且提供输出的锁存器被禁止接收和存储数据。时钟发生器切换控制线的状态，使得它们能够或禁止从主时钟信号的每个相位上的锁存器输入数据并输出数据。还公开了具有三重边沿定时的双透明锁存器。一种用于产生具有主频率的主信号并且以大于主频率的输入数据速率选择性地启用输入的方法，用于将数据输入到存储器中，并且以输入数据速率有选择地使得输出能够从存储器输出数据。

4. 发明授权

US06651176B1 Systems and methods for variable control of power dissipation in a pipelined processor 有权
标题翻译：流水线处理器功耗可变控制的系统和方法
公开(公告)号：US06651176B1
公开(公告)日：2003-11-18
申请号：US09457169
申请日：1999-12-08
申请人： Donald C. Soltis, Jr. , Glenn T. Colon-Bonet
发明人： Donald C. Soltis, Jr. , Glenn T. Colon-Bonet
IPC分类号： G06F126
CPC分类号： G06F9/3867 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F9/3836 , G06F9/3857 , G06F9/3869 , Y02D10/126 , Y02D10/152
摘要： The invention controls maximum average power dissipation by stalling high power instructions through the pipeline of a pipelined processor. A power dissipation controller stalls the high power instructions in order to control the processor's maximum average power dissipation. Preferably, the controller is modeled after a capacitive system with a constant output rate and a throttled input rate: the output rate represents the steady state maximum average power dissipation; while the input rate is stalled based upon current capacity, representing thermal response time. At start-up, the capacity is initialized. Yet for each high power instruction, the capacity increases by a weighted value. Each clock capacity is also decreased by a variable output rate. In particular, a low power operation is inserted to the stage execution circuit where the stall is desired, creating a low power state for that circuit. This stall effectively creates a “hole” at that pipeline stage, thus temporarily reducing power dissipation. The invention takes advantage of the fact that the presence of an instruction at any stage execution circuit dissipates power and that the absence (i.e., a “hole”) of an instruction at any stage dissipates less power. By controlling where and when a hole occurs within the pipeline, the maximum average power dissipation of the processor is controlled.
摘要翻译：本发明通过流水线处理器的流水线停止高功率指令来控制最大平均功耗。功耗控制器停止高功率指令，以控制处理器的最大平均功耗。优选地，控制器在具有恒定输出速率和节流输入速率的电容系统之后被建模：输出速率表示稳态最大平均功率耗散; 而输入速率则基于当前容量而停滞，代表热响应时间。启动时，容量初始化。然而对于每个大功率指令，容量增加一个加权值。每个时钟容量也以可变输出速率降低。特别地，低功率操作被插入到期望失速的级执行电路中，为该电路产生低功率状态。这个停顿在该流水线阶段有效地创建了一个“孔”，从而暂时降低功耗。本发明利用了在任何阶段执行电路中存在指令消耗功率并且任何阶段的指令的不存在（即，“孔”）消耗较少功率的事实。通过控制在管道内发生孔的何处和何时，控制处理器的最大平均功耗。

5. 发明授权

US06542093B2 Apparatus and method for reducing power and noise through reduced switching by recoding in a monotonic logic device 失效
公开(公告)号：US06542093B2
公开(公告)日：2003-04-01
申请号：US09920178
申请日：2001-08-01
申请人： Glenn T. Colon-Bonet
发明人： Glenn T. Colon-Bonet
IPC分类号： H03M700
CPC分类号： G06F7/5338
摘要： An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses monotonic logic encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a monotonic logic encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a monotonic logic encoded signal. The decode circuitry then sends the monotonic logic encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a monotonic logic encoded signal from a first logic circuit. The monotonic logic encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the monotonic logic encoded signal.

6. 发明授权

US06370639B1 Processor architecture having two or more floating-point status fields 有权
标题翻译：具有两个或多个浮点状态字段的处理器架构
公开(公告)号：US06370639B1
公开(公告)日：2002-04-09
申请号：US09169482
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F9312
CPC分类号： G06F9/3865 , G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

7. 发明授权

US06212539B1 Methods and apparatus for handling and storing bi-endian words in a floating-point processor 有权
标题翻译：用于在浮点处理器中处理和存储双向字的方法和装置
公开(公告)号：US06212539B1
公开(公告)日：2001-04-03
申请号：US09169483
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
IPC分类号： G06F700
CPC分类号： G06F7/768 , G06F7/483
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

8. 发明授权

US6151669A Methods and apparatus for efficient control of floating-point status register 有权
标题翻译：浮点状态寄存器的有效控制方法和装置
公开(公告)号：US6151669A
公开(公告)日：2000-11-21
申请号：US169481
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F7/00 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

9. 发明授权

US06408380B1 Execution of an instruction to load two independently selected registers in a single cycle 有权
标题翻译：执行在一个周期内加载两个独立选择的寄存器的指令
公开(公告)号：US06408380B1
公开(公告)日：2002-06-18
申请号：US09316446
申请日：1999-05-21
申请人： Jerome C. Huck , Glenn T. Colon-Bonet , Alan H. Karp , David A. Fotland , Dean A. Mulla
发明人： Jerome C. Huck , Glenn T. Colon-Bonet , Alan H. Karp , David A. Fotland , Dean A. Mulla
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/30098 , G06F9/384
摘要： Method and apparatus for storing and executing an instruction to load two independent registers with two values is disclosed. In one embodiment, a computer-readable medium is encoded with an instruction including an opcode field specifying that the instruction is an instruction to load two independent registers with a first value and a second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value; a second target register field specifying a second target register to load with the second value. A system to execute the instruction is also disclosed.
摘要翻译：公开了用于存储和执行用于加载具有两个值的两个独立寄存器的指令的方法和装置。在一个实施例中，计算机可读介质用包括指定该指令是用于加载具有第一值和第二值的两个独立寄存器的指令的指令进行编码，指定第一值和第二值的源字段指定第一目标寄存器以第一值加载的第一目标寄存器字段; 指定第二目标寄存器的第二目标寄存器字段，以加载第二值。还公开了执行该指令的系统。

10. 发明授权

US5404324A Methods and apparatus for performing division and square root computations in a computer 失效
标题翻译：在计算机中执行划分和平方根计算的方法和装置
公开(公告)号：US5404324A
公开(公告)日：1995-04-04
申请号：US146895
申请日：1993-11-01
申请人： Glenn T. Colon-Bonet
发明人： Glenn T. Colon-Bonet
IPC分类号： G06F7/38 , G06F7/483 , G06F7/52 , G06F7/535 , G06F7/537 , G06F7/552
CPC分类号： G06F7/535 , G06F7/5375 , G06F7/5525 , G06F2207/5528 , G06F7/4873 , G06F7/49957
摘要： An apparatus for performing floating-point division and square root computations according to an IEEE rounding standard includes input data alignment circuitry, core iteration circuitry, remainder compare circuitry, and round and select circuitry. The core iteration circuitry includes digit selector circuitry; remainder registers; quotient logic circuitry; remainder formation circuitry; and quotient registers for storing the quotient Q, incremented quotient Q+1, and decremented quotient Q-1. The remainder formation circuitry produces sum and carry bits of the P.sub.j+1 term, which are in turn fed back to the partial remainder registers and used in subsequent iterations. The quotient logic circuitry builds the quotient Q and maintains the respective quotient Q, Q+1, Q-1 registers. The outputs of these registers are fed back to the quotient logic circuitry for use in subsequent iterations. The remainder compare circuitry comprises a remainder comparator and a logic circuit. The remainder comparator receives the sum and carry bits for the P.sub.j+1 terms and outputs the "Sign" and "Zero" bits. These bits are received by the logic circuit along with a rounding mode signal, which is indicative of the selected rounding mode, e.g., shifted or normalized round to nearest, round to zero, or round to infinity. The logic circuit outputs a round select signal that selects a quotient select signal for selecting, as the final rounded quotient, the output of one of the quotient registers Q, Q+1, or Q-1. The round and select circuitry includes a round block for positive remainders and a round block for negative remainders.
摘要翻译：用于根据IEEE舍入标准执行浮点分割和平方根计算的装置包括输入数据对准电路，核心迭代电路，余数比较电路以及循环和选择电路。核心迭代电路包括数字选择器电路; 余数寄存器; 商逻辑电路; 余数形成电路; 以及用于存储商Q，递增商Q + 1和递减商Q-1的商寄存器。剩余形成电路产生Pj + 1项的和和进位位，这些位又反馈到部分余数寄存器并用于后续迭代。商逻辑电路构建商Q并维持相应的商Q，Q + 1，Q-1寄存器。这些寄存器的输出反馈到商逻辑电路，用于后续迭代。剩余比较电路包括余数比较器和逻辑电路。剩余比较器接收和并携带Pj + 1项的位，并输出“符号”和“零”位。这些位由逻辑电路连同舍入模式信号一起被接收，舍入模式信号指示所选择的舍入模式，例如，移位或归一化到最接近，最近到零，或者到达到无穷大。逻辑电路输出一个圆选择信号，其选择商选择信号，用于选择商寄存器Q，Q + 1或Q-1之一的输出作为最终舍入商。圆形和选择电路包括用于正残余物的圆形块和用于负余留物的圆形块。

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