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1. 发明授权

US06370639B1 Processor architecture having two or more floating-point status fields 有权
标题翻译：具有两个或多个浮点状态字段的处理器架构
公开(公告)号：US06370639B1
公开(公告)日：2002-04-09
申请号：US09169482
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F9312
CPC分类号： G06F9/3865 , G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

2. 发明授权

US06212539B1 Methods and apparatus for handling and storing bi-endian words in a floating-point processor 有权
标题翻译：用于在浮点处理器中处理和存储双向字的方法和装置
公开(公告)号：US06212539B1
公开(公告)日：2001-04-03
申请号：US09169483
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
IPC分类号： G06F700
CPC分类号： G06F7/768 , G06F7/483
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

3. 发明授权

US6151669A Methods and apparatus for efficient control of floating-point status register 有权
标题翻译：浮点状态寄存器的有效控制方法和装置
公开(公告)号：US6151669A
公开(公告)日：2000-11-21
申请号：US169481
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F7/00 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

4. 发明授权

US06578059B1 Methods and apparatus for controlling exponent range in floating-point calculations 有权
标题翻译：用于控制浮点运算中指数范围的方法和装置
公开(公告)号：US06578059B1
公开(公告)日：2003-06-10
申请号：US09169669
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
IPC分类号： G06F748
CPC分类号： G06F9/3865 , G06F7/483 , G06F7/49905 , G06F7/49942 , G06F9/30014 , G06F9/30094 , G06F9/30101 , G06F9/30105 , G06F9/30123 , G06F2207/382
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译：计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。每个状态字段都包含标志和控制信息。不同的浮点运算可能与不同的状态字段相关联。浮点状态寄存器的子字段可以在操作期间动态更新。替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。浮点数据可以以大端或小端格式存储。

5. 发明授权

US06301705B1 System and method for deferring exceptions generated during speculative execution 有权
标题翻译：用于推迟在投机执行期间产生的异常的系统和方法
公开(公告)号：US06301705B1
公开(公告)日：2001-10-09
申请号：US09164327
申请日：1998-10-01
申请人： Gautam B. Doshi , Peter Markstein , Alan H. Karp , Jerome C. Huck , Glenn T. Colon-Bonet , Michael Morrison
发明人： Gautam B. Doshi , Peter Markstein , Alan H. Karp , Jerome C. Huck , Glenn T. Colon-Bonet , Michael Morrison
IPC分类号： G06F945
CPC分类号： G06F9/3865 , G06F9/3842
摘要： The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative. The system further includes circuitry configured to assess each of the speculative instructions to determine whether it generates an exception. Finally, the system further includes circuitry configured to encode a deferred exception token (DET) into an unused register value of a register of the (CPU.
摘要翻译：本发明一般涉及用于支持对包括非投机和推测指令的中央处理单元（CPU）的指令集的推测性执行的系统和方法。根据本发明的一个方面，一种方法包括以下步骤：评估程序的指令以确定各个指令是推测性还是非推测性的，并且评估每个推测性指令以确定其是否产生异常。对于产生异常的每个推测性指令，该方法然后将延迟异常令牌（DET）编码为CPU的寄存器的未使用的寄存器值。根据本发明的另一方面，提供了一种系统，该系统包括被配置为评估指令集的指令以确定各个指令是推测性还是非推测性的电路。系统还包括被配置为评估每个推测性指令以确定其是否产生异常的电路。最后，系统还包括被配置为将延迟异常令牌（DET）编码为（CPU的）寄存器的未使用寄存器值的电路。

6. 发明申请

US20110055469A1 Providing State Storage In A Processor For System Management Mode 有权
标题翻译：在系统管理模式的处理器中提供状态存储
公开(公告)号：US20110055469A1
公开(公告)日：2011-03-03
申请号：US12550737
申请日：2009-08-31
申请人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G06F12/06
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态管理模式（SMM）。以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。描述和要求保护其他实施例。

7. 发明授权

US07035891B2 Reduced-hardware soft error detection 失效
标题翻译：降低硬件软错误检测
公开(公告)号：US07035891B2
公开(公告)日：2006-04-25
申请号：US10228432
申请日：2002-08-27
申请人： Sivakumar Makineni , Gautam B. Doshi
发明人： Sivakumar Makineni , Gautam B. Doshi
IPC分类号： G06F11/16
CPC分类号： G06F11/0751 , G06F11/0721
摘要： A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.
摘要翻译：提供了一种方法和系统，用于在不使用冗余逻辑的情况下执行整数加减运算的软错误检测。对于整数加法和减法，补偿逻辑利用算术逻辑单元（ALU）结果和操作数产生补偿值。补偿值由验证逻辑针对预定值确认，以确定是否发生软错误。这种补偿逻辑和验证逻辑对整数操作数和ALU产生的结果无冗余的进位传播硬件进行操作。

8. 发明授权

US08593960B2 Providing a bufferless transport method for multi-dimensional mesh topology 失效
标题翻译：为多维网状拓扑提供无缓冲传输方法
公开(公告)号：US08593960B2
公开(公告)日：2013-11-26
申请号：US12827495
申请日：2010-06-30
申请人： Michael Kauschke , Gautam B. Doshi
发明人： Michael Kauschke , Gautam B. Doshi
IPC分类号： H04L12/26 , H04L12/28 , H04L12/54 , G06F15/16 , G06F15/173 , G06F3/00
CPC分类号： H04L47/826 , H04L45/06 , H04L47/50 , H04L49/00 , H04L49/109 , H04L49/1584 , H04L49/3063 , H04L49/90
摘要： In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定在节点的输入/输出（I / O）电路中接收的分组是否发往该节点的方法，如果是，则将分组提供给I / O电路并且确定I / O电路的入口队列中是否存在一个或多个分组，并且如果是，则根据与业务流独立的全局调度将选择的分组提供给第一或第二输出寄存器。描述和要求保护其他实施例。

9. 发明授权

US08578138B2 Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode 有权
标题翻译：在进入系统管理模式时，将活动状态存储在处理器的内部存储器中，而不是在SMRAM中
公开(公告)号：US08578138B2
公开(公告)日：2013-11-05
申请号：US12550737
申请日：2009-08-31
申请人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G06F9/48
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态管理模式（SMM）。以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。描述和要求保护其他实施例。

10. 发明申请

US20140050224A1 PROVIDING A BUFFERLESS TRANSPORT METHOD FOR MULTI-DIMENSIONAL MESH TOPOLOGY 审中-公开
标题翻译：提供一种用于多维网格拓扑的无缓冲传输方法
公开(公告)号：US20140050224A1
公开(公告)日：2014-02-20
申请号：US14063858
申请日：2013-10-25
申请人： Michael Kauschke , Gautam B. Doshi
发明人： Michael Kauschke , Gautam B. Doshi
IPC分类号： H04L12/911 , H04L12/863
CPC分类号： H04L47/826 , H04L45/06 , H04L47/50 , H04L49/00 , H04L49/109 , H04L49/1584 , H04L49/3063 , H04L49/90
摘要： In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定在节点的输入/输出（I / O）电路中接收的分组是否发往该节点的方法，如果是，则将分组提供给I / O电路并且确定I / O电路的入口队列中是否存在一个或多个分组，并且如果是，则根据与业务流独立的全局调度将选择的分组提供给第一或第二输出寄存器。描述和要求保护其他实施例。

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