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1. 发明授权

US5071054A Fabrication of cast articles from high melting temperature superalloy compositions 失效
标题翻译：从高熔点高温合金组合物制造铸件
公开(公告)号：US5071054A
公开(公告)日：1991-12-10
申请号：US629856
申请日：1990-12-18
申请人： Robert Dzugan , Stephen J. Ferrigno , William R. Young , Marc J. Froning
发明人： Robert Dzugan , Stephen J. Ferrigno , William R. Young , Marc J. Froning
IPC分类号： B22D21/06 , B22D29/00 , B23K9/04 , B23K20/02 , B23P6/04 , B30B5/02 , C21D10/00 , C23C24/08
CPC分类号： B23P6/007 , B23K20/021 , C21D10/00 , Y10T29/49318
摘要： A superalloy article is fabricated by casting a high melting temperature superalloy composition and then refurbishing the primary defects that are found in the surface of the cast piece. The article is refurbished by excising the primary defects and a surrounding portion of metal by grinding, filling the excised volume with metal of the same composition as the cast article by welding or a similar technique, smoothing the surface around any resulting filler metal defects, and applying a cladding powder to the surface from which the filler metal defects are removed. The cladding powder is applied by painting a binder onto the surface and then dusting cladding powder onto the binder before it has dried. The cladding powder is a mixture of particles of a high melting temperature superalloy and particles of a lower melting temperature metal. The article is heated to a preselected temperature, depending on the alloy, to melt and subsequently solidify the cladding powder. Finally, the article is hot isostatically pressed to achieve final closure of surface defects.

2. 发明授权

US4830934A Alloy powder mixture for treating alloys 失效
标题翻译：用于处理合金的合金粉末混合物
公开(公告)号：US4830934A
公开(公告)日：1989-05-16
申请号：US56175
申请日：1987-06-01
申请人： Stephen J. Ferrigno , Mark Somerville , William R. Young
发明人： Stephen J. Ferrigno , Mark Somerville , William R. Young
IPC分类号： B23K1/00 , B22F1/00 , B22F7/08 , B23K35/30 , C22C19/05
CPC分类号： B23K35/304 , B23K35/30 , Y10T29/49746 , Y10T428/12861 , Y10T428/12931 , Y10T428/12944
摘要： An improved mixture of alloy powders is provied for use in treating a preselected article alloy, for example, to repair or join multiple components of the article. The mixture has at least three distinct groups of alloy powders which together define a mixture composition range, with each alloy powder of the groups characterized by a composition and melting range different from the others and from the article alloy. In a preferred form, the mixture composition range comprises, by weight, 15-30% Cr, 1.5-6% W, 0.4-4% Al, 1-11% Ti, 1-6% Ta, up to 1.5% B, up to 0.5% Si, up to 0.2% Zr, up to 3% Mo, up to 0.3% Hf, up to 6% Cb, up to 2% Re, with the balance selected from Co and Ni along with incidental impurities.

3. 发明授权

US07084481B2 Symmetric inducting device for an integrated circuit having a ground shield 有权
公开(公告)号：US07084481B2
公开(公告)日：2006-08-01
申请号：US10855953
申请日：2004-05-28
申请人： Rex Everett Lowther , William R. Young
发明人： Rex Everett Lowther , William R. Young
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01F17/0013 , H01F27/367 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.

4. 发明授权

US06211056B1 Integrated circuit air bridge structures and methods of fabricating same 有权
标题翻译：集成电路空气桥结构及其制造方法
公开(公告)号：US06211056B1
公开(公告)日：2001-04-03
申请号：US09199292
申请日：1998-11-24
申请人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
发明人： Patrick A. Begley , William R. Young , Anthony L. Rivoli , Jose Avelino Delgado , Stephen J. Gaul
IPC分类号： H01L214763
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5221 , H01L2924/0002 , H01L2924/00
摘要： Conductive elements which provide interconnections (air bridges between circuits) and components such as capacitors and inductors may be incorporated in the devices in a manner to reduce parasitic effects in the operation of the devices while providing close spacing which enhances the performance of the devices at high frequency. Separate substrates are provided respectively having the integrated circuits formed therein and covering, preferably sealing the integrated circuits. The air bridge conductive components (interconnections, capacitors or inductors) are formed separately in the covering substrate which is assembled with the substrate having the integrated circuit as a lid which seals and packages the circuits and the conductive element or component contained in the lid. The conductive component may be separated by cavities formed in the lid substrate or in the substrate having the integrated circuit device already formed therein. Assembly may take place at temperatures lower than necessary for fusion bonding and diffusion commonly used in the fabrication of integrated circuits. Bonds which are used may be metal, oxide or plastic (polymer) bonding material.
摘要翻译：提供互连（电路之间的空气桥）和诸如电容器和电感器的部件的导电元件可以以减少器件操作中的寄生效应的方式并入器件中，同时提供紧密的间隔，这增强了器件在高处的性能频率。分别提供分离的基板，其中形成有集成电路并覆盖，优选地密封集成电路。空气桥导电部件（互连，电容器或电感器）分别形成在与具有集成电路的基板组装的覆盖基板上，该基板具有密封并封装电路和包含在盖中的导电元件或部件的盖。导电部件可以由形成在盖基板中的空腔或已经形成有集成电路器件的基板分离。组装可能发生在集成电路制造中常用的熔接和扩散所需的温度以下。使用的债券可以是金属，氧化物或塑料（聚合物）结合材料。

5. 发明授权

US5696452A Arrangement and method for improving room-temperature testability of CMOS integrated circuits optimized for cryogenic temperature operation 失效
标题翻译： CMOS半导体集成电路室温可测性的优化布置及方法，适用于低温运行
公开(公告)号：US5696452A
公开(公告)日：1997-12-09
申请号：US512323
申请日：1995-08-08
申请人： Donald F. Hemmenway , John T. Gasner , William R. Young
发明人： Donald F. Hemmenway , John T. Gasner , William R. Young
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： Room temperature-testing of an MOS field effect transistor architecture, whose parameters have been optimized for operation at cryogenic temperatures, is facilitated by applying a prescribed reverse body-to-source voltage bias, that modifies the variation of the drain-to-source current vs. gate-to-source voltage characteristic, so as to shift the gate threshold voltage to a value corresponding to the device operating at its optimally designed cryogenic temperature. The magnitude of this back bias voltage is set at a value which adds to the number of charges required to balance the gate voltage before an inversion condition is achieved. In effect, the back bias causes the depletion layer beneath the gate to be expanded into the body beneath the gate, thereby compensating for what would otherwise be depletion mode operation, if the cryogenically designed MOS device were placed at room temperature. This allows the cryogenic performance of the MOS field effect transistor to be tested at room temperature, thereby substantially reducing manufacturing cost. Upon completion of testing of the circuit to evaluate its performance at cryogenic temperatures, the back-bias is removed, so as to allow normal operation in the circuit's intended cryogenic environment.
摘要翻译： MOS场效应晶体管架构的室温测试通过施加规定的反向体对电压偏置来实现，其中参数已被优化用于在低温下的操作，该电压修正了漏 - 源电流的变化与栅极至源极电压特性相对应，以便将栅极阈值电压移动到对应于在其最佳设计的低温温度下工作的器件的值。该反偏置电压的大小被设定为在实现反转条件之前平衡栅极电压所需的电荷数量的值。实际上，背偏置导致栅极下面的耗尽层扩展到栅极下方的主体，从而补偿如果将低温设计的MOS器件放置在室温下将是耗尽模式操作。这允许在室温下测试MOS场效应晶体管的低温性能，从而显着降低制造成本。在完成电路测试以评估其在低温温度下的性能时，将去除偏压，以便允许在电路预期的低温环境中正常工作。

6. 发明授权

US5563834A Multiport memory and method 失效
标题翻译：多端口内存和方法
公开(公告)号：US5563834A
公开(公告)日：1996-10-08
申请号：US345689
申请日：1994-11-21
申请人： Charles W. T. Longway , William R. Young
发明人： Charles W. T. Longway , William R. Young
IPC分类号： G11C7/06 , G11C7/14 , G11C8/16 , G11C17/12 , G11C7/00
CPC分类号： G11C17/12 , G11C7/062 , G11C7/065 , G11C7/14 , G11C8/16
摘要： Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
摘要翻译：集成电路存储器，其位线在多个位置彼此交叉，用于对称电容耦合。还可以使用差分读出放大器只读存储器，每个单元格的每个半阵列都有一个输入。位在两半中互补存储。

7. 发明授权

US5493581A Digital down converter and method 失效
标题翻译：数字下变频器和方法
公开(公告)号：US5493581A
公开(公告)日：1996-02-20
申请号：US930170
申请日：1992-08-14
申请人： William R. Young , David B. Chester
发明人： William R. Young , David B. Chester
IPC分类号： H03D7/16 , H03H17/06 , H04B1/26 , H04B1/30 , H04J1/05 , H04Q11/04 , H04B1/10
CPC分类号： H04B1/0021 , H03D7/165 , H03H17/06 , H04B1/0003 , H04B1/26 , H04B1/30 , H04J1/05 , H04Q11/04
摘要： A digital down converter for extracting a signal from a complex digital signal wherein the real and imaginary components of the complex digital signal are each modulated to shift the center frequency of the desired signal to zero frequency, decimated digitally to limit the bandwidth of each to the bandwidth of the desired signal and filtered to alter the shape thereof. The digital down converter includes a formatter for arranging the output of the desired signal in one of multiple output formats and a controller for programmably controlling the modulation, decimation and filtering and for selecting the desired output format.
摘要翻译：一种用于从复数数字信号中提取信号的数字下变频器，其中复数数字信号的实分量和虚分量均被调制，以将期望信号的中心频率移位到零频率，数字地抽取以限制每个信号的带宽所需信号的带宽并被滤波以改变其形状。数字下变频器包括一个格式化器，用于以多种输出格式之一布置所需信号的输出，以及用于可编程地控制调制，抽取和滤波以及选择所需输出格式的控制器。

8. 发明授权

US5484665A Rotary seal member and method for making 失效
标题翻译：旋转密封件及其制造方法
公开(公告)号：US5484665A
公开(公告)日：1996-01-16
申请号：US685110
申请日：1991-04-15
申请人： Jogender Singh , Jerry D. Schell , William R. Young
发明人： Jogender Singh , Jerry D. Schell , William R. Young
IPC分类号： C23C26/00 , C23C26/02 , C23C30/00 , F01D11/00 , F01D11/08 , F16J15/28 , B52B15/00 , B63H1/26
CPC分类号： F01D11/08 , C23C26/02 , Y10S277/94 , Y10T428/12486 , Y10T428/12806 , Y10T428/12812 , Y10T428/12819 , Y10T428/12882 , Y10T428/12889 , Y10T428/12896 , Y10T428/12903
摘要： A rotary seal member, such as a gas turbine engine blade, is provided with an improved surface layer which has an elastic modulus matched with the elastic modulus of a substrate of the member. Also, the surface layer does not form a brittle intermetallic with the substrate at an intended operating temperature. In one form, the surface layer includes abrasive particles adapted to inhibit chemical reaction with the layer material. One specific example is a Ti-alloy substrate having a metallurgically bonded layer based on Nb, and including cubic boron nitride abrasive particles coated with cobalt entrapped in the layer.
摘要翻译：诸如燃气涡轮发动机叶片的旋转密封构件设置有改进的表面层，其具有与构件的基底的弹性模量匹配的弹性模量。此外，表面层在预定的工作温度下不与基底形成脆性金属间化合物。在一种形式中，表面层包括适于抑制与层材料的化学反应的磨料颗粒。一个具体实例是具有基于Nb的冶金结合层的Ti合金基底，并且包括被包覆在该层中的钴的立方氮化硼磨料颗粒。

9. 发明授权

US5341335A Decimating filter 失效
标题翻译：抽奖过滤器
公开(公告)号：US5341335A
公开(公告)日：1994-08-23
申请号：US945674
申请日：1992-09-15
申请人： William R. Young , William F. Johnstone
发明人： William R. Young , William F. Johnstone
IPC分类号： G06F7/78 , H03H17/02 , H03H17/06 , G11C8/04
CPC分类号： G06F7/785 , H03H17/0223 , H03H17/0621 , H03H2218/08
摘要： A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as FIFO registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a LIFO register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section. Each of the registers in the forward shifting and reverse shifting data sections provide an output. An ALU section operates on the outputs and provides a decimating memory output.
摘要翻译：抽取存储器包括具有可寻址存储器位置的存储器。存储器形成多个寄存器，每个寄存器包括至少一个可寻址存储器位置。多个寄存器形成前向移位数据部分和反向移位数据部分。第一解码器通过对可寻址存储器位置的读写寻址来输入和输出数据样本，将前向移位数据段中的寄存器和反向移位数据段中的除第一寄存器之外的所有寄存器作为FIFO寄存器操作。可寻址存储器位置的读和写寻址相对于彼此偏移以提供抽取因子。画笔解码器将反向移位数据部分中的第一寄存器操作为用于从前向移位数据部分接收的数据样本块内的反向排序数据样本的LIFO寄存器。正向和反向移位数据段中的每个寄存器提供输出。 ALU部分对输出进行操作，并提供抽取存储器输出。

10. 发明授权

US5265225A Digital signal processing address sequencer 失效
标题翻译：数字信号处理地址排序器
公开(公告)号：US5265225A
公开(公告)日：1993-11-23
申请号：US482803
申请日：1990-02-21
申请人： William R. Young , David H. Damerow
发明人： William R. Young , David H. Damerow
IPC分类号： G06F7/00 , G06F12/06
CPC分类号： G06F7/00
摘要： A sequencer including input structure for receiving and retaining sequential data which includes the sequence starting address, the number of blocks in the sequence, the number of words in a block, increment between blocks and increment between words, includes an adder connected between the input structure and an output device and includes a controller for selectively providing to the adders inputs one or more of the sequence starting address, increment between words, increment between blocks and the output of the output device as a function of the number of blocks in the sequence and the number of words in a block.
摘要翻译：一种定序器，包括用于接收和保持顺序数据的输入结构，其包括序列起始地址，序列中的块数，块中的字数，块之间的增量和字之间的增量，包括连接在输入结构输出设备，包括控制器，用于根据序列中的块的数量，有选择地向加法器输入提供序列起始地址，单词之间的递增，块之间的递增和输出设备的输出的一个或多个，块中的单词数。

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