专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5563834A Multiport memory and method 失效
标题翻译：多端口内存和方法
公开(公告)号：US5563834A
公开(公告)日：1996-10-08
申请号：US345689
申请日：1994-11-21
申请人： Charles W. T. Longway , William R. Young
发明人： Charles W. T. Longway , William R. Young
IPC分类号： G11C7/06 , G11C7/14 , G11C8/16 , G11C17/12 , G11C7/00
CPC分类号： G11C17/12 , G11C7/062 , G11C7/065 , G11C7/14 , G11C8/16
摘要： Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
摘要翻译：集成电路存储器，其位线在多个位置彼此交叉，用于对称电容耦合。还可以使用差分读出放大器只读存储器，每个单元格的每个半阵列都有一个输入。位在两半中互补存储。

2. 发明授权

US5440506A Semiconductor ROM device and method 失效
标题翻译：半导体ROM器件及方法
公开(公告)号：US5440506A
公开(公告)日：1995-08-08
申请号：US930930
申请日：1992-08-14
申请人： Charles W. T. Longway , William R. Young
发明人： Charles W. T. Longway , William R. Young
IPC分类号： G11C7/06 , G11C7/14 , G11C8/16 , G11C17/12 , G11C17/00
CPC分类号： G11C17/12 , G11C7/062 , G11C7/065 , G11C7/14 , G11C8/16
摘要： Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
摘要翻译：集成电路存储器，其位线在多个位置彼此交叉，用于对称电容耦合。还可以使用差分读出放大器只读存储器，每个单元格的每个半阵列都有一个输入。位在两半中互补存储。

3. 发明授权

US5586072A Multiport memory and method 失效
公开(公告)号：US5586072A
公开(公告)日：1996-12-17
申请号：US346178
申请日：1994-11-21
申请人： Charles W. T. Longway , William R. Young
发明人： Charles W. T. Longway , William R. Young
IPC分类号： G11C7/06 , G11C7/14 , G11C8/16 , G11C17/12 , G11C5/06
CPC分类号： G11C17/12 , G11C7/062 , G11C7/065 , G11C7/14 , G11C8/16
摘要： Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.

4. 发明授权

US5544095A Rom cell for a multiport memory and method 失效
标题翻译： Rom单元的多端口内存和方法
公开(公告)号：US5544095A
公开(公告)日：1996-08-06
申请号：US450879
申请日：1995-05-26
申请人： Charles W. T. Longway , William R. Young
发明人： Charles W. T. Longway , William R. Young
IPC分类号： G11C7/06 , G11C7/14 , G11C8/16 , G11C17/12 , G11C17/00
CPC分类号： G11C17/12 , G11C7/062 , G11C7/065 , G11C7/14 , G11C8/16
摘要： Integrated circuit memory with bitlines which cross each other in multiple place for symmetric capacitives coupling. Also read only memory with differential sense amplifier with an input to each half array of cells. Bits are stored complementarily in the two halves.
摘要翻译：集成电路存储器，其位线在多个位置彼此交叉，用于对称电容耦合。还可以使用差分读出放大器只读存储器，每个单元格的每个半阵列都有一个输入。位在两半中互补存储。

5. 发明授权

US5373466A Flash-clear of ram array using partial reset mechanism 失效
标题翻译：使用部分复位机制清除ram阵列
公开(公告)号：US5373466A
公开(公告)日：1994-12-13
申请号：US858310
申请日：1992-03-25
申请人： David S. Landeta , William R. Young , Charles W. T. Longway
发明人： David S. Landeta , William R. Young , Charles W. T. Longway
IPC分类号： G11C7/20 , G11C8/16 , G11C7/00
CPC分类号： G11C7/20 , G11C8/16 , Y10S257/903 , Y10S257/904
摘要： A reset mechanism for a random access memory array comprises an auxiliary reset circuit, which does not require modification of the contents of the memory itself. For a random access memory capable of storing M, N-bit words, the auxiliary mechanism includes a plurality of M reset state circuits that are respectively associated with the M words of memory. The reset state circuit preferably comprises an additional `resetable` memory cell for each word of memory, which is integrated within the structure of the memory itself. In order to reset one or more words of memory, the associated reset state circuits are placed in a reset state-representative condition. The state of each reset state circuit is used to controllably mask (e.g. is logically ANDed with) the contents of its associated word of memory, whenever that word is read out. If the reset memory cell has been cleared, then regardless of the contents of its associated word in memory, the mask will cause the addressed memory word to be output as all zeros. Whenever a new word value is written to memory, its associated reset state circuit is simultaneously accessed and a valid or non-reset representative `1` bit is stored in that reset state circuit. Subsequently, when that word is read out from memory, the (`1`) value of the mask bit stored in its associated reset cell will cause the contents of the word to be output as is.
摘要翻译：用于随机存取存储器阵列的复位机构包括辅助复位电路，其不需要修改存储器本身的内容。对于能够存储M，N位字的随机存取存储器，辅助机制包括分别与存储器的M个字相关联的多个M复位状态电路。复位状态电路优选地包括用于存储器的每个字的附加的“可复位”存储器单元，其被集成在存储器本身的结构内。为了复位一个或多个存储器字，相关的复位状态电路处于复位状态代表状态。每当读出该字时，每个复位状态电路的状态用于可控制地掩蔽（例如，与其相关联的存储器的内容的逻辑“与”）。如果复位存储单元已被清除，则无论存储器中相关字的内容如何，该掩码将使所寻址的存储器字全部输出。每当将新的字值写入存储器时，其相关的复位状态电路被同时访问，并且有效或非复位代表“1”位被存储在该复位状态电路中。随后，当从存储器中读出该字时，存储在其相关联的复位单元中的掩码位的（'1'）值将导致字的内容原样输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式