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1. 发明授权

US07667511B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US07667511B2
公开(公告)日：2010-02-23
申请号：US11195060
申请日：2005-08-02
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03K3/017
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

2. 发明申请

US20090196384A1 Direct Radio Frequency (RF) Sampling With Recursive Filtering Method 审中-公开
标题翻译：直接射频（RF）采样递归滤波方法
公开(公告)号：US20090196384A1
公开(公告)日：2009-08-06
申请号：US12334268
申请日：2008-12-12
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

3. 发明授权

US06924681B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US06924681B2
公开(公告)日：2005-08-02
申请号：US10154093
申请日：2002-05-22
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03F1/02 , H03F1/06 , H03F3/217 , H03K3/00 , H03K3/017 , H03K5/06 , H03K7/02 , H04B1/04
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

4. 发明授权

US06851493B2 Digital PLL with gear shift 有权
标题翻译：数字PLL与换档
公开(公告)号：US06851493B2
公开(公告)日：2005-02-08
申请号：US09728180
申请日：2000-12-01
申请人： Robert B. Staszewski , Kenneth J. Maggio
发明人： Robert B. Staszewski , Kenneth J. Maggio
IPC分类号： H03L7/093 , H03L7/06 , H03L7/099 , H03L7/107 , H03L7/18 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0991 , H03L7/1806
摘要： A PLL synthesizer (100) includes a gear-shifting scheme of the PLL loop gain constant, α. During frequency/phase acquisition, a larger loop gain constant, α1 is used such that the resulting phase error is within limits. After the frequency/phase gets acquired, the developed phase error, which is a rough indication of the frequency offset is in a steady-state condition. While transitioning into the tracking mode, the DC offset is added to the DCO tuning signal preferably the DC offset is added to the phase error signal and the loop constant is reduced from α1 to α2. This scheme provides for hitless operation, while requiring a low dynamic range of the phase detector (101).
摘要翻译： PLL合成器（100）包括PLL环路增益常数α的换档方案。在频率/相位采集期间，使用较大的环路增益常数α1，使得所得到的相位误差在限度内。在获取频率/相位之后，发展的相位误差是频率偏移的粗略指示处于稳态条件。当转换到跟踪模式时，DC偏移被添加到DCO调谐信号中，优选地，DC偏移被加到相位误差信号上，并且环路常数从α1减小到α2。该方案提供了无脉冲操作，同时需要相位检测器（101）的低动态范围。

5. 发明授权

US08155256B2 Method and apparatus for asynchronous clock retiming 有权
标题翻译：用于异步时钟重新定时的方法和装置
公开(公告)号：US08155256B2
公开(公告)日：2012-04-10
申请号：US09969307
申请日：2001-10-02
申请人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
发明人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
IPC分类号： H04L7/00
CPC分类号： H03L7/18 , H03L7/085 , H03L7/091 , H03L2207/50
摘要： A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.
摘要翻译：使用时间到数字转换器来确定较高频率时钟（过采样时钟）的哪个边缘比较低频率定时信号的边缘更远。同时，过采样时钟通过两个寄存器执行定时信号的采样：一个在上升沿，另一个在下降沿。然后，选择由分数阶段检测器决定确定的“更好质量”重新定时的寄存器，以提供重定时输出。

6. 发明授权

US07519135B2 Direct radio frequency (RF) sampling with recursive filtering method 有权
标题翻译：直接射频（RF）采样采用递归滤波法
公开(公告)号：US07519135B2
公开(公告)日：2009-04-14
申请号：US10190867
申请日：2002-07-08
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03K5/01
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

7. 发明授权

US08321489B2 Software reconfigurable digital phase lock loop architecture 有权
标题翻译：软件可重构数字锁相环架构
公开(公告)号：US08321489B2
公开(公告)日：2012-11-27
申请号：US11853575
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： G06F17/10
CPC分类号： H03L7/0992 , G06F7/605 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F17/10 , H03L7/1974 , H03L7/1976 , H03L2207/50 , H04B1/04 , H04W56/003
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

8. 发明申请

US20110261871A1 ALL-DIGITAL FREQUENCY SYNTHESIS WITH DCO GAIN CALCULATION 有权
标题翻译：全数字频率合成与DCO增益计算
公开(公告)号：US20110261871A1
公开(公告)日：2011-10-27
申请号：US13175594
申请日：2011-07-01
申请人： Robert B. Staszewski , Dirk Leipold , John Wallberg
发明人： Robert B. Staszewski , Dirk Leipold , John Wallberg
IPC分类号： H04B17/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。

9. 发明授权

US08027657B2 Sampling mixer with asynchronous clock and signal domains 有权
标题翻译：具有异步时钟和信号域的采样混频器
公开(公告)号：US08027657B2
公开(公告)日：2011-09-27
申请号：US10121761
申请日：2002-04-12
申请人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Yo-Chuol Ho , Dirk Leipold
IPC分类号： H04B1/26 , H04L27/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.
摘要翻译：具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。利用混频器中不同采样电容器之间的显着电容差和叠加特性。

10. 发明授权

US08000428B2 All-digital frequency synthesis with DCO gain calculation 有权
标题翻译：全数字频率合成采用DCO增益计算
公开(公告)号：US08000428B2
公开(公告)日：2011-08-16
申请号：US10302029
申请日：2002-11-22
申请人： Robert B. Staszewski , Dirk Leipold , John Wallberg
发明人： Robert B. Staszewski , Dirk Leipold , John Wallberg
IPC分类号： H04L7/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译：全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。

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