专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08321489B2 Software reconfigurable digital phase lock loop architecture 有权
标题翻译：软件可重构数字锁相环架构
公开(公告)号：US08321489B2
公开(公告)日：2012-11-27
申请号：US11853575
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： G06F17/10
CPC分类号： H03L7/0992 , G06F7/605 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F17/10 , H03L7/1974 , H03L7/1976 , H03L2207/50 , H04B1/04 , H04W56/003
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

2. 发明授权

US07936221B2 Computation spreading for spur reduction in a digital phase lock loop 有权
标题翻译：在数字锁相环中用于锐减的计算扩展
公开(公告)号：US07936221B2
公开(公告)日：2011-05-03
申请号：US11853588
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： H03L7/06
CPC分类号： H03L7/1806 , G06F1/04 , H03J1/0008 , H03L7/085 , H03L2207/50
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.
摘要翻译：一种新颖有用的装置和使用数字锁相环（DPLL）架构中的计算扩展的杂散减少方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于将原子操作的计算扩展到整个PLL参考时钟周期内并在整个PLL参考时钟周期内完成。每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这个功能可以显着地减少由计算产生的每个周期的电流瞬变。此外，电流瞬变的频率内容处于较高的处理器时钟频率。这导致在输出光谱的敏感部分内杂散的显着减少。

3. 发明申请

US20090070568A1 Computation parallelization in software reconfigurable all digital phase lock loop 有权
标题翻译：软件中的计算并行化可重构所有数字锁相环
公开(公告)号：US20090070568A1
公开(公告)日：2009-03-12
申请号：US11949310
申请日：2007-12-03
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： G06F9/38
CPC分类号： G06F9/3004 , G06F9/30003 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F9/345 , G06F9/3875 , G06F9/3885 , G06F9/3897 , H03L7/085 , H03L7/091 , H03L7/1806 , H03L7/1974 , H03L2207/50
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。基于多级数据流的处理器集成了经过优化的并行/流水线架构，以有效地执行数据流处理。多级并行/流水线处理器通过组合多个RCU来提供显着更高的处理速度，其中输入数据样本与所有RCU并行输入，而来自一个RCU的计算结果由相邻的下游RCU使用。寄存器文件为历史值提供存储，而每个RCU中的本地存储为临时结果提供存储。

4. 发明申请

US20080072025A1 Software reconfigurable digital phase lock loop architecture 有权
标题翻译：软件可重构数字锁相环架构
公开(公告)号：US20080072025A1
公开(公告)日：2008-03-20
申请号：US11853575
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： G06F9/302 , G06F9/44
CPC分类号： H03L7/0992 , G06F7/605 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F17/10 , H03L7/1974 , H03L7/1976 , H03L2207/50 , H04B1/04 , H04W56/003
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。 RCU以足够快的处理器时钟速率提供时钟，以确保所有PLL原子操作在单个PLL参考时钟周期内执行。

5. 发明授权

US08134411B2 Computation spreading utilizing dithering for spur reduction in a digital phase lock loop 有权
标题翻译：计算扩展利用抖动在数字锁相环中进行锐减
公开(公告)号：US08134411B2
公开(公告)日：2012-03-13
申请号：US12104778
申请日：2008-04-17
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： H03L7/06
CPC分类号： H03L1/022
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.
摘要翻译：一种用于数字锁相环（DPLL）架构中使用抖动的计算扩展的杂散减少的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于在PLL参考时钟周期内扩展原子操作的计算，其中每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这显着地减少了由计算产生的每个周期的电流瞬变。电流瞬变的频率内容处于更高的处理器时钟频率，这导致输出频谱的敏感部分内的杂散的显着减少。通过对原子操作的软件循环的持续时间进行抖动和/或通过在软件循环的每次迭代内随机混洗一个或多个非依赖于数据的指令来实现毛刺的进一步减少。

6. 发明授权

US07809927B2 Computation parallelization in software reconfigurable all digital phase lock loop 有权
标题翻译：软件中的计算并行化可重构所有数字锁相环
公开(公告)号：US07809927B2
公开(公告)日：2010-10-05
申请号：US11949310
申请日：2007-12-03
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30003 , G06F9/30014 , G06F9/30032 , G06F9/30181 , G06F9/345 , G06F9/3875 , G06F9/3885 , G06F9/3897 , H03L7/085 , H03L7/091 , H03L7/1806 , H03L7/1974 , H03L2207/50
摘要： A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results.
摘要翻译：一种基于软件的锁相环（PLL）的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）包括其指令被优化以执行PLL的原子操作的指令集。基于多级数据流的处理器集成了经过优化的并行/流水线架构，以有效地执行数据流处理。多级并行/流水线处理器通过组合多个RCU来提供显着更高的处理速度，其中输入数据样本与所有RCU并行输入，而来自一个RCU的计算结果由相邻的下游RCU使用。寄存器文件为历史值提供存储，而每个RCU中的本地存储为临时结果提供存储。

7. 发明申请

US20080069286A1 Computation spreading for spur reduction in a digital phase lock loop 有权
标题翻译：在数字锁相环中用于锐减的计算扩展
公开(公告)号：US20080069286A1
公开(公告)日：2008-03-20
申请号：US11853588
申请日：2007-09-11
申请人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
发明人： Roman Staszewski , Robert B. Staszewski , Fuqiang Shi
IPC分类号： H03L7/06
CPC分类号： H03L7/1806 , G06F1/04 , H03J1/0008 , H03L7/085 , H03L2207/50
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.
摘要翻译：一种新颖有用的装置和使用数字锁相环（DPLL）架构中的计算扩展的杂散减少方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于将原子操作的计算扩展到整个PLL参考时钟周期内并在整个PLL参考时钟周期内完成。每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这个功能可以显着地减少由计算产生的每个周期的电流瞬变。此外，电流瞬变的频率内容处于较高的处理器时钟频率。这导致在输出光谱的敏感部分内杂散的显着减少。

8. 发明申请

US20090262877A1 Computation spreading utilizing dithering for spur reduction in a digital phase lock loop 有权
标题翻译：计算扩展利用抖动在数字锁相环中进行锐减
公开(公告)号：US20090262877A1
公开(公告)日：2009-10-22
申请号：US12104778
申请日：2008-04-17
申请人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
发明人： Fuqiang Shi , Roman Staszewski , Robert B. Staszewski
IPC分类号： H03L7/06 , G06F9/44
CPC分类号： H03L1/022
摘要： A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.
摘要翻译：一种用于数字锁相环（DPLL）架构中使用抖动的计算扩展的杂散减少的新颖有用的装置和方法。基于软件的PLL集成了可重新配置的计算单元（RCU），该单元经过优化和编程，可以以时间分配方式顺序执行PLL或任何其他所需任务的所有原子操作。结合RCU的应用特定指令集处理器（ASIP）适于在PLL参考时钟周期内扩展原子操作的计算，其中每个计算以比PLL参考时钟速率高得多的处理器时钟频率执行。这显着地减少了由计算产生的每个周期的电流瞬变。电流瞬变的频率内容处于更高的处理器时钟频率，这导致输出频谱的敏感部分内的杂散的显着减少。通过对原子操作的软件循环的持续时间进行抖动和/或通过在软件循环的每次迭代内随机混洗一个或多个非依赖于数据的指令来实现毛刺的进一步减少。

9. 发明申请

US20130121044A1 Power Converter Controller IC Having Pins with Multiple Functions 有权
标题翻译：具有多功能引脚的电源转换器控制器IC
公开(公告)号：US20130121044A1
公开(公告)日：2013-05-16
申请号：US13612607
申请日：2012-09-12
申请人： Xiaolin Gao , Yong Li , Qiu Sha , Fuqiang Shi , John William Kesterson , Jiang Chen
发明人： Xiaolin Gao , Yong Li , Qiu Sha , Fuqiang Shi , John William Kesterson , Jiang Chen
IPC分类号： H02H7/12
CPC分类号： H02M1/32 , H02M3/33523
摘要： A controller integrated circuit (IC) for controlling a power converter uses one or more IC pins having plurality of functions such as configuration of a parameter supported by the controller IC and shutdown protection. Several different functions may be supported by a single IC pin, thereby reducing the number of pins required in the controller IC and also reducing the cost of manufacturing the controller IC. The controller IC may also share a comparison circuit among different pins and the different functions provided by those pins. Use of a shared comparison circuit further reduces the cost of manufacturing the controller IC without sacrificing the performance of the IC.
摘要翻译：用于控制功率转换器的控制器集成电路（IC）使用具有多个功能的一个或多个IC引脚，诸如由控制器IC支持的参数的配置和关断保护。单个IC引脚可以支持几个不同的功能，从而减少了控制器IC中所需的引脚数量，并且还降低了制造控制器IC的成本。控制器IC还可以在不同引脚之间共享比较电路以及由这些引脚提供的不同功能。使用共享比较电路进一步降低了制造控制器IC的成本，而不牺牲IC的性能。

10. 发明申请

US20100164455A1 ADAPTIVE MULTI-MODE DIGITAL CONTROL IMPROVING LIGHT-LOAD EFFICIENCY IN SWITCHING POWER CONVERTERS 有权
标题翻译：自适应多模数字控制提高开关电源转换器的光负载效率
公开(公告)号：US20100164455A1
公开(公告)日：2010-07-01
申请号：US12608854
申请日：2009-10-29
申请人： Yong Li , Carrie Seim , Junjie Zheng , John W. Kesterson , Liang Yan , Clarita Poon , Fuqiang Shi
发明人： Yong Li , Carrie Seim , Junjie Zheng , John W. Kesterson , Liang Yan , Clarita Poon , Fuqiang Shi
IPC分类号： G05F1/10
CPC分类号： H02M3/157 , H02M2001/0032 , Y02B70/16
摘要： Adaptive multi-mode digital control schemes that improve the light-load efficiency (and thus the overall average efficiency) in switch-mode power converters without causing performance issues such as audible noises or excessive voltage ripples. Embodiments include a switch-mode power converter that reduces current in the power converter using a second pulse-width-modulation (PWM) mode before reaching switching frequencies that generate audible noises. As the load across the output of the power converter is reduced, the power converter transitions from a first PWM mode in high load conditions to a first pulse-frequency-modulation (PFM) mode, then to a second PWM mode, and finally to a second PFM mode. During the second PFM mode, the switching frequency is dropped to audible frequency levels. Current in the power converter, however, is reduced in the second PWM mode before transitioning to the second PFM mode. Therefore, the power converter produces less or no audible noise in light load conditions where the switching frequency drops to audible frequency levels, while achieving high efficiency across varying load conditions.
摘要翻译：自适应多模数字控制方案，可以提高开关模式电源转换器的轻负载效率（从而提高整体平均效率），而不会引起诸如声音噪声或电压波动过大等性能问题。实施例包括开关模式功率转换器，其在达到产生可听见噪声的开关频率之前，使用第二脉冲宽度调制（PWM）模式减小功率转换器中的电流。随着功率转换器输出端的负载减小，功率转换器从高负载条件下的第一个PWM模式转换到第一个脉冲频率调制（PFM）模式，然后转换到第二个PWM模式，最后到第二PFM模式。在第二个PFM模式下，开关频率下降到可听频率水平。然而，在转换到第二PFM模式之前，功率转换器中的电流在第二PWM模式中减小。因此，功率转换器在轻负载条件下产生较少或没有可听见的噪声，其中开关频率下降到可听频率水平，同时在不同的负载条件下实现高效率。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式