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1. 发明申请

US20090196384A1 Direct Radio Frequency (RF) Sampling With Recursive Filtering Method 审中-公开
标题翻译：直接射频（RF）采样递归滤波方法
公开(公告)号：US20090196384A1
公开(公告)日：2009-08-06
申请号：US12334268
申请日：2008-12-12
申请人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Kenneth J. Maggio , Dirk Leipold
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
摘要翻译：具有采样混合器1100的无线电接收机2000，用于通过用历史和旋转电容器1111和1112直接采样RF电流来产生离散时间采样流，其中读出旋转电容器上的累积电荷以产生样本。混合器通过预测毛刺的发生（或检测观察到的和预测的样品之间的显着差异）并为损坏的样品产生校正的样品来提供对噪声毛刺的免疫。这些校正样本可以用专用电路1933（数字）或混合器1100（模拟）来创建。

2. 发明授权

US06366420B1 Method of restoring the orientation of a pinned layer of a magnetoresistive head 有权
标题翻译：恢复磁阻头的钉扎层的取向的方法
公开(公告)号：US06366420B1
公开(公告)日：2002-04-02
申请号：US09617070
申请日：2000-07-16
申请人： Indumini W. Ranmuthu , Kenneth J. Maggio
发明人： Indumini W. Ranmuthu , Kenneth J. Maggio
IPC分类号： G11B503
CPC分类号： G11B5/02 , G11B5/012 , G11B2005/0008 , G11B2005/0018
摘要： Magnetoresistive, MR, heads and giant magnetoresistive, GMR, heads are used in hard disk drive storage systems. The heads have a pinned layer whose magnetic orientation, if incorrect, gives rise to data read errors. A pinned layer reset method and circuit is provided to restore the magnetic orientation of the pinned layer by applying a reset pulse to the MR head. The circuit employs the existing low frequency cutoff capacitor in the initial amplification stage of the preamplifier to charge the magnitude of the reset pulse. The magnitude of the pulse is programmable by selecting bits in the existing write current digital to analog converter. The head select input transistor applies the pulse to the MR head. The pulse width is programmable as is the discharge rate. The settling value of the pulse is determined by the existing read current digital to analog converter value. The method of the invention is applicable to preamplifiers designed as current bias preamplifiers and to preamplifiers designed as voltage bias amplifiers.
摘要翻译：磁阻，MR，磁头和巨磁阻，GMR，磁头用于硬盘驱动器存储系统。头部具有钉扎层，其磁性取向（如果不正确）导致数据读取错误。提供钉扎层复位方法和电路以通过向MR头施加复位脉冲来恢复被钉扎层的磁性取向。该电路在前置放大器的初始放大级中使用现有的低频截止电容器对复位脉冲的幅度充电。通过选择现有写入电流数模转换器中的位来编程脉冲幅度。磁头选择输入晶体管将脉冲施加到MR磁头。脉冲宽度可以按照放电速率进行编程。脉冲的稳定值由现有的读取电流数模转换器值决定。本发明的方法适用于设计为电流偏置前置放大器的前置放大器和设计为电压偏置放大器的前置放大器。

3. 发明授权

US06275092B1 Active damping circuit 有权
标题翻译：主动阻尼电路
公开(公告)号：US06275092B1
公开(公告)日：2001-08-14
申请号：US09441000
申请日：1999-11-16
申请人： Kenneth J. Maggio , Patrick M. Teterud
发明人： Kenneth J. Maggio , Patrick M. Teterud
IPC分类号： H03K1756
CPC分类号： G11B5/022 , G11B5/012 , G11B5/09
摘要： An active damping circuit damps the ringing effect caused by a write circuit for a disk drive. The circuit includes upper switches and lower switched current sources. A capacitive feedback is connected between the output and the lower switched current sources.
摘要翻译：主动阻尼电路可以抑制由磁盘驱动器的写入电路引起的振铃效应。电路包括上开关和下开关电流源。电容反馈连接在输出和下切换电流源之间。

4. 发明授权

US06924681B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US06924681B2
公开(公告)日：2005-08-02
申请号：US10154093
申请日：2002-05-22
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03F1/02 , H03F1/06 , H03F3/217 , H03K3/00 , H03K3/017 , H03K5/06 , H03K7/02 , H04B1/04
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

5. 发明授权

US06851493B2 Digital PLL with gear shift 有权
标题翻译：数字PLL与换档
公开(公告)号：US06851493B2
公开(公告)日：2005-02-08
申请号：US09728180
申请日：2000-12-01
申请人： Robert B. Staszewski , Kenneth J. Maggio
发明人： Robert B. Staszewski , Kenneth J. Maggio
IPC分类号： H03L7/093 , H03L7/06 , H03L7/099 , H03L7/107 , H03L7/18 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0991 , H03L7/1806
摘要： A PLL synthesizer (100) includes a gear-shifting scheme of the PLL loop gain constant, α. During frequency/phase acquisition, a larger loop gain constant, α1 is used such that the resulting phase error is within limits. After the frequency/phase gets acquired, the developed phase error, which is a rough indication of the frequency offset is in a steady-state condition. While transitioning into the tracking mode, the DC offset is added to the DCO tuning signal preferably the DC offset is added to the phase error signal and the loop constant is reduced from α1 to α2. This scheme provides for hitless operation, while requiring a low dynamic range of the phase detector (101).
摘要翻译： PLL合成器（100）包括PLL环路增益常数α的换档方案。在频率/相位采集期间，使用较大的环路增益常数α1，使得所得到的相位误差在限度内。在获取频率/相位之后，发展的相位误差是频率偏移的粗略指示处于稳态条件。当转换到跟踪模式时，DC偏移被添加到DCO调谐信号中，优选地，DC偏移被加到相位误差信号上，并且环路常数从α1减小到α2。该方案提供了无脉冲操作，同时需要相位检测器（101）的低动态范围。

6. 发明授权

US5959417A Current feedback amplifier having trimcircuitry and method for controlling and equalizing stator winding current 失效
标题翻译：具有微调电路的电流反馈放大器和用于控制和均衡定子绕组电流的方法
公开(公告)号：US5959417A
公开(公告)日：1999-09-28
申请号：US937219
申请日：1997-09-18
申请人： Kenneth J. Maggio , Rolf Lagerquist
发明人： Kenneth J. Maggio , Rolf Lagerquist
IPC分类号： H02P6/00 , H02P6/08 , H02P7/06 , H02P7/10 , H02K23/00
CPC分类号： H02P6/085 , H02P6/28
摘要： A current feedback amplifier (12) is provided for controlling a stator winding phase current in a polyphase stator winding, such as a three-phase stator winding (10), of a polyphase direct current motor. The current amplifier (12) includes a first stage current feedback amplifier C (27) and a second stage current feedback amplifier (100) coupled through a switch (101). The first stage current feedback amplifier C (27) detects a stator winding phase current I.sub.AB flowing through a C-coil (15) of the three-phase stator winding (10) and generates an equalized sense current I.sub.senseT in response that is related to I.sub.AB. The equalized sense current I.sub.senseT is generated using a phase trim FET (31) and an adjustable phase trim FET (32). The second stage current feedback amplifier (100) receives I.sub.senseT from the first stage current feedback amplifier C (27) and generates a control signal. This may be done by comparing I.sub.senseT to an amplitude adjusted reference current I.sub.refT. The amplitude adjusted reference current I.sub.refT is generated using an amplitude trim FET (81) and an adjustable amplitude trim FET (82). The second stage current feedback amplifier (100) provides the control signal to a driver circuit for controlling the stator winding phase current. The second stage current feedback amplifier (100) may sequentially or commutatively couple to other first stage current sense amplifiers, such as a first stage current feedback amplifier B (30) or a first stage current feedback amplifier A (28), to control other stator winding phase currents to generate equalized, amplitude adjusted stator winding phase currents.
摘要翻译：提供电流反馈放大器（12），用于控制多相直流电动机的多相定子绕组（例如三相定子绕组（10））中的定子绕组相电流。电流放大器（12）包括通过开关（101）耦合的第一级电流反馈放大器C（27）和第二级电流反馈放大器（100）。第一级电流反馈放大器C（27）检测流过三相定子绕组（10）的C线圈（15）的定子绕组相电流IAB，并响应于IAB产生相等的感测电流IsenseT 。使用相位调整FET（31）和可调节相位调整FET（32）产生均衡的感测电流IsenseT。第二级电流反馈放大器（100）从第一级电流反馈放大器C（27）接收IsenseT，并产生控制信号。这可以通过将IsenseT与调幅参考电流IrefT进行比较来完成。使用幅度调整FET（81）和可调节幅度修正FET（82）产生幅度调整的参考电流IrefT。第二级电流反馈放大器（100）将控制信号提供给用于控制定子绕组相电流的驱动电路。第二级电流反馈放大器（100）可以顺序地或互换地耦合到诸如第一级电流反馈放大器B（30）或第一级电流反馈放大器A（28）的其它第一级电流检测放大器，以控制其它定子绕组相电流产生均衡的调幅定子绕组相电流。

7. 发明授权

US08155256B2 Method and apparatus for asynchronous clock retiming 有权
标题翻译：用于异步时钟重新定时的方法和装置
公开(公告)号：US08155256B2
公开(公告)日：2012-04-10
申请号：US09969307
申请日：2001-10-02
申请人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
发明人： Robert B. Staszewski , Kenneth J. Maggio , Dirk D. Leipold
IPC分类号： H04L7/00
CPC分类号： H03L7/18 , H03L7/085 , H03L7/091 , H03L2207/50
摘要： A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.
摘要翻译：使用时间到数字转换器来确定较高频率时钟（过采样时钟）的哪个边缘比较低频率定时信号的边缘更远。同时，过采样时钟通过两个寄存器执行定时信号的采样：一个在上升沿，另一个在下降沿。然后，选择由分数阶段检测器决定确定的“更好质量”重新定时的寄存器，以提供重定时输出。

8. 发明授权

US07003276B2 Subsampling communication receiver architecture with gain control and RSSI generation 有权
标题翻译：采样增益控制和RSSI生成的通信接收机架构
公开(公告)号：US07003276B2
公开(公告)日：2006-02-21
申请号：US10132025
申请日：2002-04-25
申请人： Khurram Muhammad , Dirk Leipold , Kenneth J. Maggio
发明人： Khurram Muhammad , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H04B1/26
CPC分类号： H04B1/0025 , H03H15/00 , H03H19/004 , H04B1/0003 , H04B1/28 , H04L27/24
摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform. The samples can be manipulated to provide gain adjustment to the second voltage waveform. The samples are obtained by charging a sampling capacitance in response to a current waveform that corresponds to the first voltage waveform. The use of different sampling capacitances during respective predetermined time intervals permits the signal strength of the first waveform to be determined from observation of the second waveform.
摘要翻译：第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。将样品组合以产生第二电压波形。可以操作样品以对第二电压波形提供增益调整。通过响应于对应于第一电压波形的电流波形对采样电容进行充电来获得样本。在各个预定时间间隔期间使用不同的采样电容允许通过观察第二波形来确定第一波形的信号强度。

9. 发明授权

US06282044B1 8V ring clamp circuit 有权
标题翻译： 8V环形钳位电路
公开(公告)号：US06282044B1
公开(公告)日：2001-08-28
申请号：US09286187
申请日：1999-04-05
申请人： Patrick M. Teterud , Kenneth J. Maggio
发明人： Patrick M. Teterud , Kenneth J. Maggio
IPC分类号： G11B502
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B2005/0013
摘要： A clamp circuit for clamping a terminal of an H-bridge circuit. The clamp circuit is capable of being applied to a voltage in excess of 5V including 8 volts.
摘要翻译：用于钳位H桥电路端子的钳位电路。钳位电路能够施加到超过5V的电压，包括8伏特。

10. 发明授权

US07667511B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US07667511B2
公开(公告)日：2010-02-23
申请号：US11195060
申请日：2005-08-02
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03K3/017
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

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