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1. 发明授权

US07493417B2 Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system 失效
标题翻译：用于在多处理器系统中使用处理器互连的微处理器通信的方法和数据处理系统
公开(公告)号：US07493417B2
公开(公告)日：2009-02-17
申请号：US10318515
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/16
CPC分类号： G06F15/167
摘要： Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs utilizing communication over the specialized bus, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：处理器通信寄存器（PCR）包含在多处理器系统中的每个处理器中并由专用总线互连提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器利用专用总线上的通信在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据内的变化，并绕过高速缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

2. 发明授权

US07818364B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
标题翻译：基于群集的多处理器系统中微处理器通信的方法和数据处理系统
公开(公告)号：US07818364B2
公开(公告)日：2010-10-19
申请号：US11952479
申请日：2007-12-07
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

3. 发明授权

US07356568B2 Method, processing unit and data processing system for microprocessor communication in a multi-processor system 失效
标题翻译：用于多处理器系统中微处理器通信的方法，处理单元和数据处理系统
公开(公告)号：US07356568B2
公开(公告)日：2008-04-08
申请号：US10318514
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F13/00
CPC分类号： G06F9/30101
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

4. 发明授权

US07698373B2 Method, processing unit and data processing system for microprocessor communication in a multi-processor system 失效
标题翻译：用于多处理器系统中微处理器通信的方法，处理单元和数据处理系统
公开(公告)号：US07698373B2
公开(公告)日：2010-04-13
申请号：US11971959
申请日：2008-01-10
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F13/00
CPC分类号： G06F9/30101
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率无限流的加载，存储和无效命令。

5. 发明授权

US07734877B2 Method and data processing system for processor-to-processor communication in a clustered multi-processor system 失效
标题翻译：用于集群多处理器系统中处理器到处理器通信的方法和数据处理系统
公开(公告)号：US07734877B2
公开(公告)日：2010-06-08
申请号：US11954686
申请日：2007-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F13/00
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

6. 发明申请

US20080155231A1 METHOD AND DATA PROCESSING SYSTEM FOR PROCESSOR-TO-PROCESSOR COMMUNICATION IN A CLUSTERED MULTI-PROCESSOR SYSTEM 失效
标题翻译：集成多处理器系统中处理器到处理器通信的方法和数据处理系统
公开(公告)号：US20080155231A1
公开(公告)日：2008-06-26
申请号：US11954686
申请日：2007-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F9/00
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

7. 发明授权

US07360067B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network 有权
标题翻译：基于群集的多处理器无线网络中微处理器通信的方法和数据处理系统
公开(公告)号：US07360067B2
公开(公告)日：2008-04-15
申请号：US10318513
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/173
CPC分类号： G06F15/173 , H04W28/14
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

8. 发明授权

US07359932B2 Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效
标题翻译：基于群集的多处理器系统中微处理器通信的方法和数据处理系统
公开(公告)号：US07359932B2
公开(公告)日：2008-04-15
申请号：US10318516
申请日：2002-12-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译：包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存系统具有无限的加载流，存储和无效命令。

9. 发明授权

US07089364B2 System and method to stall dispatch of gathered store operations in a store queue using a timer 失效
标题翻译：使用定时器将存储队列中收集的存储操作分派的系统和方法停止
公开(公告)号：US07089364B2
公开(公告)日：2006-08-08
申请号：US10825188
申请日：2004-04-15
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Hugh Shen , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Hugh Shen , Derek Edward Williams
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F12/0804
摘要： A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.
摘要翻译：一种方法和处理器系统，其基本上增强了存储队列条目的存储收集能力，以便能够在该条目被选择用于发送之前收集最大数量的接近时间存储操作。为每个条目提供一个计数器，以跟踪从上次收集到条目的时间。当计数器达到阈值饱和点之前没有发生新的聚合时，该信号将被发出准备就绪。通过在计数器到期之前定义最佳阈值饱和点，为入口提供足够的时间来收集即时存储操作。当某些条件发生时，该条目可能被视为有资格进行选择，包括条目变满，发出屏障操作和计数器饱和。计数器的使用增加了存储队列条目完成收集足够的存储操作以在将该条目分派到RC机器之前更新整个高速缓存行的能力。

10. 发明授权

US07047320B2 Data processing system providing hardware acceleration of input/output (I/O) communication 有权
标题翻译：数据处理系统提供输入/输出（I / O）通讯的硬件加速
公开(公告)号：US07047320B2
公开(公告)日：2006-05-16
申请号：US10339724
申请日：2003-01-09
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F3/00
CPC分类号： G06F13/124 , G06F12/0835
摘要： An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.
摘要翻译：诸如处理单元的集成电路包括衬底和形成在衬底中的集成电路。集成电路包括执行指令的处理器核心，耦合到处理器核心的互连接口，其支持处理器核心与集成电路外部的系统互连之间的通信，以及外部通信适配器的至少一部分，耦合通过输入/输出通信链路支持输入/输出通信的处理器核心。

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