专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100262808A1 MANAGING INSTRUCTIONS FOR MORE EFFICIENT LOAD/STORE UNIT USAGE 有权
标题翻译：管理更有效的装载/存储单元使用说明
公开(公告)号：US20100262808A1
公开(公告)日：2010-10-14
申请号：US12420143
申请日：2009-04-08
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3836 , G06F11/348 , G06F2201/88 , Y02D10/34
摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
摘要翻译：本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。加载/存储单元在端口接收第一条指令。响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。当第一位被激活时，指令排序单元阻止重新发行的第一条指令。处理器单元确定第一指令的拒绝类。指令排序单元启动定时器。定时器的长度取决于第一条指令的拒绝类型。指令排序单元重置响应定时器超时的第一位。响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。

2. 发明授权

US08271765B2 Managing instructions for more efficient load/store unit usage 有权
标题翻译：管理更有效的加载/存储单元使用说明
公开(公告)号：US08271765B2
公开(公告)日：2012-09-18
申请号：US12420143
申请日：2009-04-08
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Dung Quoc Nguyen , Bruce Joseph Ronchetti
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/3824 , G06F9/3836 , G06F11/348 , G06F2201/88 , Y02D10/34
摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.
摘要翻译：本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。加载/存储单元在端口接收第一条指令。响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。当第一位被激活时，指令排序单元阻止重新发行的第一条指令。处理器单元确定第一指令的拒绝类。指令排序单元启动定时器。定时器的长度取决于第一条指令的拒绝类型。指令排序单元重置响应定时器超时的第一位。响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。

3. 发明申请

US20100180081A1 Adaptive Data Prefetch System and Method 失效
标题翻译：自适应数据预取系统和方法
公开(公告)号：US20100180081A1
公开(公告)日：2010-07-15
申请号：US12354219
申请日：2009-01-15
申请人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
IPC分类号： G06F12/08 , G06F1/32 , G06F12/00
CPC分类号： G06F12/0862 , G06F1/3203 , G06F12/0897 , G06F2212/6022
摘要： A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.
摘要翻译：数据处理系统包括处理器，包括多级缓存，预取系统和存储器的单元。数据处理系统可以在第一模式和第二模式中操作。预取系统可以响应于由外部代理设置的所需功耗策略或基于片上功率/性能阈值的硬件自动地改变行为。

4. 发明授权

US08156287B2 Adaptive data prefetch 失效
标题翻译：自适应数据预取
公开(公告)号：US08156287B2
公开(公告)日：2012-04-10
申请号：US12354219
申请日：2009-01-15
申请人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
发明人： Pradip Bose , Alper Buyuktosunoglu , Miles Robert Dooley , Michael Stephen Floyd , David Scott Ray , Bruce Joseph Ronchetti
IPC分类号： G06F13/00 , G06F1/00
CPC分类号： G06F12/0862 , G06F1/3203 , G06F12/0897 , G06F2212/6022
摘要： A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power consumption policy set by an external agent or automatically via hardware based on on-chip power/performance thresholds.
摘要翻译：数据处理系统包括处理器，包括多级缓存，预取系统和存储器的单元。数据处理系统可以在第一模式和第二模式中操作。预取系统可以响应于由外部代理设置的所需功耗策略或基于片上功率/性能阈值的硬件自动地改变行为。

5. 发明授权

US08001394B2 Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes 有权
标题翻译：多核微处理器的功能管理和控制方法和系统，通过每小时可编程电源模式进行
公开(公告)号：US08001394B2
公开(公告)日：2011-08-16
申请号：US12023536
申请日：2008-01-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.
摘要翻译：提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。小巧包括处理器核心和相关联的存储器高速缓存。功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。电源管理控制微架构根据功率设置设置微体系结构电源管理技术。全球电源管理控制器发出第一个命令。全局功率管理控制器可以驻留在微处理器上或者关闭。全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。每个小穗可以设置为分开的功率水平。

6. 发明申请

US20100268975A1 On-Chip Power Proxy Based Architecture 有权
标题翻译：基于片上功率代理的架构
公开(公告)号：US20100268975A1
公开(公告)日：2010-10-21
申请号：US12424161
申请日：2009-04-15
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
IPC分类号： G06F1/26
CPC分类号： G06F11/348 , G06F11/3006 , G06F11/3024 , G06F11/3062 , G06F2201/88 , Y02D10/34
摘要： A method for estimating power consumption within a multi-core microprocessor chip is provided. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
摘要翻译：提供了一种用于估计多核微处理器芯片内的功耗的方法。授权用户选择要监视的一组活动。一组活动的每个活动的值存储在一组计数器的单独计数器中，形成一组存储的值。该值包括计数乘以活动特有的权重因子。该组活动被分组成子集。将对应于每个子集中的每个活动的存储值相加，形成每个子集的总值。每个子集的总值乘以与子集对应的因子，形成每个子集的缩放值。将每个子集的缩放值相加，形成功率使用值。功率管理器基于功率使用值与阈值的比较来调整单元的操作参数。

7. 发明授权

US08271809B2 On-chip power proxy based architecture 有权
标题翻译：基于片上功率代理的架构
公开(公告)号：US08271809B2
公开(公告)日：2012-09-18
申请号：US12424161
申请日：2009-04-15
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd
IPC分类号： G06F1/26 , G06F1/28 , G06F1/32
CPC分类号： G06F11/348 , G06F11/3006 , G06F11/3024 , G06F11/3062 , G06F2201/88 , Y02D10/34
摘要： Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.
摘要翻译：说明性实施例估计多核微处理器芯片内的功率消耗。授权用户选择要监视的一组活动。一组活动的每个活动的值存储在一组计数器的单独计数器中，形成一组存储的值。该值包括计数乘以活动特有的权重因子。该组活动被分组成子集。将对应于每个子集中的每个活动的存储值相加，形成每个子集的总值。每个子集的总值乘以与子集对应的因子，形成每个子集的缩放值。将每个子集的缩放值相加，形成功率使用值。功率管理器基于功率使用值与阈值的比较来调整单元的操作参数。

8. 发明授权

US08261276B2 Power-efficient thread priority enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US08261276B2
公开(公告)日：2012-09-04
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46 , G06F9/00 , G06F13/28 , G06F1/32
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

9. 发明授权

US08650413B2 On-chip power proxy based architecture 失效
标题翻译：基于片上功率代理的架构
公开(公告)号：US08650413B2
公开(公告)日：2014-02-11
申请号：US12749179
申请日：2010-03-29
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Maria Lorena Pesantez
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael Stephen Floyd , Maria Lorena Pesantez
IPC分类号： G06F1/32 , G06F1/26 , G06F9/00
CPC分类号： G06F1/3203 , G06F11/3062 , G06F11/3096 , Y02D10/126
摘要： The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.
摘要翻译：这些实施例提供了第一组计数器的分配的计数器，并且存储形成一组存储值的一组活动的活动的值。该值包括计数乘以活动特有的权重因子。功率管理器管理第一组计数器，接收一组要监视单元的活动，基于每个活动的发生频率和每个活动的功耗中的至少一个，将该部分分组成子集，将所存储的对应于每个子集中的每个活动的值以达到每个子集的总值，将每个子集的总值乘以与该子集对应的因子，以形成每个子集的缩放值，并且将每个子集的缩放值相加以形成电力使用价值。

10. 发明申请

US20090249349A1 Power-Efficient Thread Priority Enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US20090249349A1
公开(公告)日：2009-10-01
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式