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1. 发明授权

US06472267B2 DRAM cell having storage capacitor contact self-aligned to bit lines and word lines 失效
公开(公告)号：US06472267B2
公开(公告)日：2002-10-29
申请号：US10007110
申请日：2001-12-03
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L218242
CPC分类号： H01L27/10852
摘要： A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer (46) over the source region (18) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region (18).

2. 发明授权

US5557122A Semiconductor electrode having improved grain structure and oxide growth properties 失效
标题翻译：具有改善的晶粒结构和氧化物生长特性的半导体电极
公开(公告)号：US5557122A
公开(公告)日：1996-09-17
申请号：US438956
申请日：1995-05-12
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L21/02 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/49 , H01L29/51 , H01L27/108 , H01L29/788
CPC分类号： H01L27/1085 , H01L21/28273 , H01L28/40 , H01L29/4916 , H01L29/511 , H01L29/66825
摘要： The use of nitrogen doped amorphous silicon as an electrode material for a semiconductor integrated circuit is described. A preferred embodiment is a single transistor flash EPROM cell is disclosed having a tunnel dielectric (202), a floating gate (206), an intergate dielectric having three layers (208, 210, 212), and a control gate (218). The floating gate (206) is composed of in-situ nitrogen doped amorphous silicon. Due to the nitrogen doping the floating gate (206) retains its microcrystalline structure under high temperatures, eliminating large grain boundaries in the floating gate (206). As a result, arrays composed of the disclosed EPROM cell have improved memory cell threshold (V.sub.TM) distributions. In addition, silicon oxide grown from the the floating gate (206) has fewer stress induced defects reducing leakage paths that contribute to data retention errors.An alternate embodiment uses nitrogen doped amorphous silicon as the capacitor plates (304 and 306) in a DRAM cell (300). The nitrogen doped amorphous silicon oxidizes at a slower rate than undoped amorphous silicon and has less inherent stress resulting in thinner a capacitor dielectric (308) of fewer defects. The capacitor plates (304 and 306) maintain their microcrystalline structure throughout subsequent temperature cycling resulting in increased capacitor area.
摘要翻译：描述了使用氮掺杂非晶硅作为半导体集成电路的电极材料。公开了一种单晶体管闪存EPROM单元，其具有隧道电介质（202），浮动栅极（206），具有三层（208,210,212）和控制栅极（218）的隔间电介质。浮栅（206）由原位氮掺杂的非晶硅组成。由于氮掺杂，浮置栅极（206）在高温下保持其微晶结构，从而消除了浮动栅极（206）中的大晶界。结果，由所公开的EPROM单元组成的阵列具有改善的存储单元阈值（VTM）分布。此外，从浮动栅极（206）生长的氧化硅具有较少的应力诱发缺陷，减少了有助于数据保留误差的泄漏路径。替代实施例使用氮掺杂非晶硅作为DRAM单元（300）中的电容器板（304和306）。氮掺杂的非晶硅以比未掺杂的非晶硅更慢的速率氧化，并且具有较少的固有应力，导致较少缺陷的电容器电介质（308）更薄。电容器板（304和306）在随后的温度循环中保持其微晶结构，导致增加的电容器面积。

3. 发明授权

US6133602A Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures 有权
公开(公告)号：US6133602A
公开(公告)日：2000-10-17
申请号：US448272
申请日：1999-11-24
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/72
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer. The discharge path allows charge to travel from the second conductive layer through the via to the first conductive layer. From the first conductive layer the charge can travel to the substrate through a buried contact structure.

4. 发明授权

US06392267B1 Flash EPROM array with self-aligned source contacts and programmable sector erase architecture 失效
标题翻译：闪存EPROM阵列具有自对准源触点和可编程扇区擦除架构
公开(公告)号：US06392267B1
公开(公告)日：2002-05-21
申请号：US08845752
申请日：1997-04-25
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L29788
CPC分类号： H01L27/11519 , G11C16/08 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： A flash EPROM array (100) and method of manufacture is disclosed. Source regions (118a-118f) are shared between the memory cells (108a,l-108d,n) of row (104a-104d) pairs, and are isolated from one another in the row direction by isolation regions 120. Low resistance source conductor members (122a-122b) extend in the row direction and are formed over the source regions (118a-118f) and make contact therewith in a self-aligned fashion. The architecture allows for source decoding and thus enables user programmable sector erase architecture.
摘要翻译：公开了一种闪存EPROM阵列（100）及其制造方法。源极区（118a-118f）在行（104a-104d）对的存储单元（108a，1-108d，n）之间共享，并且通过隔离区120在行方向上彼此隔离。低电阻源极构件（122a-122b）在行方向上延伸并且形成在源区域（118a-118f）上并且以自对准的方式与其接触。该架构允许源解码，从而实现用户可编程扇区擦除架构。

5. 发明授权

US5994730A DRAM cell having storage capacitor contact self-aligned to bit lines and word lines 失效
公开(公告)号：US5994730A
公开(公告)日：1999-11-30
申请号：US754391
申请日：1996-11-21
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852
摘要： A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer (46) over the source region (18) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region (18).

6. 发明授权

US5701264A Dynamic random access memory cell having increased capacitance 失效
标题翻译：具有增加的电容的动态随机存取存储器单元
公开(公告)号：US5701264A
公开(公告)日：1997-12-23
申请号：US792460
申请日：1997-01-31
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87
摘要： A dynamic random access memory cell and method of fabrication thereof are disclosed. An access transistor (10) is formed in a substrate (12). The deposition of a first dielectric layer (20) follows. A plurality of conductive layers (22-30) are deposited, with alternating layers (24 and 28) having a higher dopant concentration than the other layers (22, 26 and 30). A contact hole (32) is etched through the conductive layers (22-30) and the first dielectric layer (20) to the substrate (12). A contact layer (36) is then deposited, making contact with the substrate (12) and each conductive layer (22-30). The conductive layers (22-30) and contact layer (36) are patterned with an isotropic etch selective to the higher doped layers (24 and 28). The resulting structure is a conductive member (42) with a peripheral side surface (44) having inset furrows (40) formed by the selective etching of the higher doped layers (24 and 28). A conformal capacitor dielectric (46) is formed over the conductive structure (42). A conductive plate layer (46) is formed over the capacitor dielectric (46).
摘要翻译：公开了一种动态随机存取存储单元及其制造方法。在衬底（12）中形成存取晶体管（10）。遵循第一介电层（20）的沉积。沉积多个导电层（22-30），交替层（24和28）具有比其它层（22,26和30）更高的掺杂剂浓度。通过导电层（22-30）和第一介电层（20）蚀刻到基板（12）上的接触孔（32）。然后沉积接触层（36），与衬底（12）和每个导电层（22-30）接触。导电层（22-30）和接触层（36）被图案化为对较高掺杂层（24和28）选择性的各向同性蚀刻。所得到的结构是具有通过选择性蚀刻较高掺杂层（24和28）而形成的插入沟（40）的周边侧表面（44）的导电构件（42）。在导电结构（42）之上形成保形电容器电介质（46）。导电板层（46）形成在电容器电介质（46）的上方。

7. 发明授权

US06589834B1 Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current 有权
标题翻译：半导体芯片将DRAM单元与外围电路隔离，并减少电池漏电流
公开(公告)号：US06589834B1
公开(公告)日：2003-07-08
申请号：US09848627
申请日：2001-05-03
申请人： Chitranjan N. Reddy , Ritu Shrivastava
发明人： Chitranjan N. Reddy , Ritu Shrivastava
IPC分类号： H01L218238
CPC分类号： H01L21/761 , H01L27/10897
摘要： The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.
摘要翻译：半导体芯片中的动态随机存取存储器（DRAM）单元通过在衬底中直接形成DRAM单元而将周边和其它功能电路形成在与衬底隔离的阱中而与外围电路隔离。除了提供隔离之外，DRAM单元的放置还减少了单元中的漏电流，从而增加了DRAM单元可以在不刷新的情况下保持电荷的时间。

8. 发明授权

US06373089B1 DRAM cell having storage capacitor contact self-aligned to bit lines and word lines 失效
标题翻译：具有存储电容器的DRAM单元与位线和字线自对准
公开(公告)号：US06373089B1
公开(公告)日：2002-04-16
申请号：US09637322
申请日：2000-08-10
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L27108
CPC分类号： H01L27/10852
摘要： A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer (46) over the source region (18) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region (18).
摘要翻译：公开了具有与字线和位线自对准的电容器 - 位位线（COB）结构的DRAM单元（10）。字线（24）和位线（28）由包括绝缘侧壁的绝缘结构形成。字线绝缘结构包括在源极区域（18）上延伸的蚀刻阻挡层（46）。第一层间电介质（ILD）（48）使字线（24）与位线（28）绝缘，并且第二ILD（60）使位线与单元电容器绝缘。通过蚀刻穿过第一和第二ILD（48和60）来形成与位线和字线自对准的电容器接触孔（34），以在源极区域（18）上暴露蚀刻阻挡层（46））。通过蚀刻暴露的位线和字线的部分由它们各自的绝缘结构保护。在源极区（18）上的暴露的蚀刻阻挡层（46）被清除，并且形成具有延伸到接触孔中以与源极区（18）接触的接触的存储电容器。

9. 发明授权

US5731606A Reliable edge cell array design 失效
标题翻译：可靠的边缘单元阵列设计
公开(公告)号：US5731606A
公开(公告)日：1998-03-24
申请号：US454750
申请日：1995-05-31
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L27/105 , H01L27/10
CPC分类号： H01L27/105 , Y10S257/923 , Y10S257/925
摘要： Techniques are provided for protecting the cells of an array against deleterious effects of, for example, photolithography, etching and charge contamination. The cell array is designed to have edge cells modified at layout, or inactive edge cells, or guardrings surrounding the active array to contain the above effects, leaving the active cells highly reliable and with identical behavior.
摘要翻译：提供了用于保护阵列的电池免受例如光刻，蚀刻和电荷污染的有害影响的技术。单元阵列被设计为具有在布局或非活动边缘单元处修改的边缘单元或围绕有源阵列的保护以包含上述效果，使活动单元高度可靠并具有相同的行为。

10. 发明授权

US6020237A Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures 失效
标题翻译：减少在堆叠栅极结构的制造中由于充电引起的介电损伤的方法
公开(公告)号：US6020237A
公开(公告)日：2000-02-01
申请号：US18775
申请日：1998-02-04
申请人： Ritu Shrivastava , Chitranjan N. Reddy
发明人： Ritu Shrivastava , Chitranjan N. Reddy
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer. The discharge path allows charge to travel from the second conductive layer through the via to the first conductive layer. From the first conductive layer the charge can travel to the substrate through a buried contact structure.
摘要翻译：制造结构以减少由于充电引起的电介质损伤的方法很容易被纳入现有的堆叠栅极制造工艺中。图案化导电层以形成通过电流传递器件耦合到衬底的结构。每个电流通过器件与控制栅极结构隔离到蚀刻工艺的结束，从而在基本上所有堆叠的栅极蚀刻步骤中为控制栅极结构提供放电路径。用一个或多个掩模对第一和第二导电层进行构图以产生堆叠的栅极结构。多个掩模在蚀刻过程期间最小化第二导电层的暴露面积，并且因此减小栅极结构上的充电量。每个电流通过装置优选地是通过将第二导电层耦合到第一导电层的互连。放电路径允许电荷从第二导电层通过通孔行进到第一导电层。从第一导电层开始，电荷可通过掩埋接触结构行进到衬底。

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