专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07360177B1 Method and arrangement providing for implementation granularity using implementation sets 有权
标题翻译：使用实现集提供实现粒度的方法和布置
公开(公告)号：US07360177B1
公开(公告)日：2008-04-15
申请号：US10913000
申请日：2004-08-06
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
摘要翻译：基于用于集成电路设计的用户设计的实现集抽象的设计层次结构包括多个节点和多个节点中的每个节点的定义，其描述了包含在每个节点中的元素的类型和所定义的层级通过每个节点。每个节点可以包括设计的至少一个实现元素，并且可以在包括一组逻辑元素，一组放置元素以及一组放置和路由元素的组中选择该至少一个实现元素。

2. 发明授权

US07181704B1 Method and system for designing integrated circuits using implementation directives 有权
标题翻译：使用实施指令设计集成电路的方法和系统
公开(公告)号：US07181704B1
公开(公告)日：2007-02-20
申请号：US10913746
申请日：2004-08-06
申请人： Daniel J. Downs , Raymond Kong , John J. Laurence , Sankaranarayanan Srinivasan , Richard Yachyang Sun
发明人： Daniel J. Downs , Raymond Kong , John J. Laurence , Sankaranarayanan Srinivasan , Richard Yachyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.
摘要翻译：使用用于流量控制的实施指令来设计集成电路的方法可以包括加载设计以及指定约束的步骤，创建由部分网表形成的数据结构的至少一个实例，并且分解至少一组高级别规则到简单的实施指令。该方法还可以包括以下步骤：将简单实施指令有选择地附加到数据结构，实现查询数据结构节点以创建要在数据结构上执行的任务列表的任务管理器，以及使用通用流引擎。

3. 发明授权

US08296690B1 Method and arrangement providing for implementation granularity using implementation sets 有权
标题翻译：使用实现集提供实现粒度的方法和布置
公开(公告)号：US08296690B1
公开(公告)日：2012-10-23
申请号：US12027501
申请日：2008-02-07
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasen
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasen
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.
摘要翻译：基于用于集成电路设计的用户设计的实现集抽象的设计层次结构包括多个节点和多个节点中的每个节点的定义，其描述了包含在每个节点中的元素的类型和所定义的层级通过每个节点。每个节点可以包括设计的至少一个实现元素，并且可以在包括一组逻辑元素，一组放置元素以及一组放置和路由元素的组中选择该至少一个实现元素。

4. 发明授权

US07146583B1 Method and system for implementing a circuit design in a tree representation 有权
标题翻译：在树形表示中实现电路设计的方法和系统
公开(公告)号：US07146583B1
公开(公告)日：2006-12-05
申请号：US10912999
申请日：2004-08-06
申请人： Richard Yachyang Sun , Daniel J. Downs , Raymond Kong , John J. Laurence
发明人： Richard Yachyang Sun , Daniel J. Downs , Raymond Kong , John J. Laurence
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method of implementing a user integrated circuit (IC) design in a tree representation includes the step of introducing the tree representation for the user IC design in a partitioned manner including at least one sub-design to form a design abstraction of the user design. At least one sub-design can include a sub-design providing for multiple levels of implementation hierarchy. The method can further include the step of traversing the design abstraction in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for at least one sub-design, and the step of traversing the design abstraction in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs. Traversing the design abstraction in the bottom-up fashion can facilitate a re-budgeting of timing for the integrated circuit design.
摘要翻译：在树形表示中实现用户集成电路（IC）设计的方法包括以包括至少一个子设计的分区方式引入用户IC设计的树表示以形成用户设计的设计抽象的步骤。至少一个子设计可以包括提供多级实现层次的子设计。该方法还可以包括以自顶向下的方式遍历设计抽象以提供从至少一个子设计的楼层规划，端口分配和时间预算中选择的功能的步骤，以及遍历设计抽象的步骤自下而上的方式，以促进资源冲突的解决和多个子设计的并行处理中的至少一个。以自下而上的方式遍历设计抽象可以有助于对集成电路设计的时序进行重新预算。

5. 发明授权

US08141010B1 Method and arrangement providing for implementation granularity using implementation sets 有权
公开(公告)号：US08141010B1
公开(公告)日：2012-03-20
申请号：US12028337
申请日：2008-02-08
申请人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
发明人： Raymond Kong , Daniel J. Downs , John J. Laurence , Richard Yachyang Sun , Sankaranarayanan Srinivasan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

6. 发明授权

US07290241B1 Method and system for managing behavior of algorithms 有权
标题翻译：用于管理算法行为的方法和系统
公开(公告)号：US07290241B1
公开(公告)日：2007-10-30
申请号：US10913752
申请日：2004-08-06
申请人： Daniel J. Downs , John D. Bunte , Raymond Kong , John J. Laurence , Richard Yachyang Sun
发明人： Daniel J. Downs , John D. Bunte , Raymond Kong , John J. Laurence , Richard Yachyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.
摘要翻译：一种管理算法行为的方法包括指定管理I-Set实现指令，命令行选项和环境变量的管理规则/策略，并将管理规则/策略加载到行为管理器中。在客户端工具中，I-Set层次结构一次处理并迭代一个I-Set节点。没有更多的I-Sets要处理，该方法就完成了。如果更多，那么该工具将使用具有查询行为的符号指示符的I-Set查询“行为管理器”。行为管理器可以回复客户端工具，指示是否在I-Set节点的相应逻辑上支持查询行为。如果I-Set节点的算法缺少查询行为，则另一个I-Set可能需要处理。如果I-Set节点的算法具有查询行为，则客户端工具将相应的算法应用于适当的逻辑。

7. 发明授权

US07171644B1 Implementation set-based guide engine and method of implementing a circuit design 有权
标题翻译：实现集导向引擎和实现电路设计的方法
公开(公告)号：US07171644B1
公开(公告)日：2007-01-30
申请号：US10912957
申请日：2004-08-06
申请人： John J. Laurence , Daniel J. Downs , Raymond Kong , Richard Yachyang Sun
发明人： John J. Laurence , Daniel J. Downs , Raymond Kong , Richard Yachyang Sun
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.
摘要翻译：实现集成电路设计的方法可以包括形成基本实现集合并形成具有多个指导实施集节点的指导实现集的步骤。该方法还可以包括以下步骤：在多个指导实施集节点中的至少一个引导实施集节点（或每个节点）上存储指令。该方法还可以包括以下步骤：在多个指导实施集节点中的至少一个指导实施集节点（或每个节点）上创建和存储任务。该方法还可以包括在引导实现集树中的每个节点被访问时调用在指导实现集合节点上存储的每个任务的步骤。

8. 发明授权

US06732349B1 Method and apparatus for improving PIP coverage in programmable logic devices 有权
标题翻译：用于改善可编程逻辑器件中的PIP覆盖的方法和装置
公开(公告)号：US06732349B1
公开(公告)日：2004-05-04
申请号：US10231900
申请日：2002-08-29
申请人： Richard Yachyang Sun , Sandor S. Kalman , Sudip K. Nag
发明人： Richard Yachyang Sun , Sandor S. Kalman , Sudip K. Nag
IPC分类号： G06F1750
CPC分类号： G01R31/318516 , G01R31/31704 , G06F17/5077
摘要： Routing algorithms can be modified to increase the number of programmable interconnect points (PIPs) used in a routing pattern. A file is set up to store information on whether a PIP has been covered. The cost of a node can be decreased by a predetermined value if two nodes are connected by an uncovered PIP. In another embodiment, a file is set up to store a count for each PIP. The count is increased each time the PIP is used in a routing. The cost of a node can be increased by multiplying a predetermined value and the count of a PIP associated with the node.
摘要翻译：可以修改路由算法以增加在路由模式中使用的可编程互连点数（PIP）。设置一个文件来存储PIP是否被覆盖的信息。如果两个节点通过未覆盖的PIP连接，节点的成本可以降低预定值。在另一个实施例中，设置文件以存储每个PIP的计数。每次在路由中使用PIP时，计数都会增加。可以通过将预定值与与节点相关联的PIP的计数相乘来增加节点的成本。

9. 发明授权

US6134516A Simulation server system and method 失效
标题翻译：仿真服务器系统及方法
公开(公告)号：US6134516A
公开(公告)日：2000-10-17
申请号：US19384
申请日：1998-02-05
申请人： Steven Wang , Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Ren-Song Tsay , Richard Yachyang Sun , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai
发明人： Steven Wang , Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Ren-Song Tsay , Richard Yachyang Sun , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/5027
摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. A Simulation server in accordance with an embodiment of the present invention allows multiple users to access the same reconfigurable hardware unit to effectively simulate and accelerate the same or different user designs in a time-shared manner in both a network and a non-network environment. The server provides the multiple users or processes to access the reconfigurable hardware unit for acceleration and hardware state swapping purposes. The Simulation server includes the scheduler, one or more device drivers, and the reconfigurable hardware unit. The scheduler in the Simulation server is based on a preemptive round robin algorithm. The server scheduler includes a simulation job queue table, a priority sorter, and a job swapper.
摘要翻译： SEMulation系统提供四种操作模式：（1）软件仿真，（2）通过硬件加速模拟，（3）在线仿真（ICE）和（4）后仿真分析。在高水平上，本发明可以以上述四种模式或这些模式的各种组合来体现。这些模式的核心是控制该系统整体运行的软件内核。内核的主控制循环执行以下步骤：初始化系统，评估主动测试台过程/组件，评估时钟组件，检测时钟边沿，更新寄存器和存储器，传播组合组件，提前模拟时间，并继续循环只要存在有效的测试台过程。根据本发明的实施例的仿真服务器允许多个用户访问相同的可重配置硬件单元，以在网络和非网络环境中以时间共享的方式有效地模拟和加速相同或不同的用户设计。服务器提供多个用户或进程来访问可重新配置的硬件单元，以实现加速和硬件状态交换的目的。模拟服务器包括调度程序，一个或多个设备驱动程序和可重新配置的硬件单元。模拟服务器中的调度器基于抢占式循环算法。服务器调度程序包括模拟作业队列表，优先级排序器和作业交换器。

10. 发明授权

US6009256A Simulation/emulation system and method 失效
公开(公告)号：US6009256A
公开(公告)日：1999-12-28
申请号：US850136
申请日：1997-05-02
申请人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Richard Yachyang Sun , Mike Mon Yen Tsai , Ren-Song Tsay , Steven Wang
发明人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Richard Yachyang Sun , Mike Mon Yen Tsai , Ren-Song Tsay , Steven Wang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5027 , G06F17/5022
摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. Each mode or combination of modes provides the following main features or combinations of main features: (1) switching among modes, manually or automatically; (2) compilation process to generate software models and hardware models; (3) component type analysis for generating hardware models; (4) software clock set-up to avoid race conditions through, in one embodiment, gated clock logic analysis and gated data logic analysis; (5) software clock implementation through, in one embodiment, clock edge detection in the software model to trigger an enable signal in the hardware model, send signal from the primary clock to the clock input of the clock edge register in the hardware model via the gated clock logic, send a clock enable signal to the enable input of the hardware model's register, send data from the primary clock register to the hardware model's register via the gated data logic, and reset the clock edge register disabling the clock enable signal to the enable input of the hardware model's registers; (6) log selective data for debug sessions and post-simulation analysis; and (7) combinational logic regeneration.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式