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    • 1. 发明授权
    • Equalization circuit
    • 均衡电路
    • US07742520B2
    • 2010-06-22
    • US11367660
    • 2006-03-03
    • Richard SimpsonRuediger Kuhn
    • Richard SimpsonRuediger Kuhn
    • H03H7/30
    • H04L7/033H04B3/06H04L25/03031H04L25/03885H04L2025/03681
    • An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether the edges between bits in the data waveform are early or late. Adjusting the equalization causes edges to appear in the same place, whereas if the adjustment is incorrect certain edges will be late and certain edges will be early depending on the history of “1”s and “0”s in the data stream. This is an effect of so-called intersymbol interference. The control mechanism includes circuits for recognizing patterns of “1”s and “0”s in the recent history of the data waveform whose occurrence is used to trigger the adjustment of the equalizer.
    • 特别是允许传输线进行低通滤波的均衡电路包括根据数据波形中的位之间的边缘是早还是晚的控制的补偿均衡器。 调整均衡会使边缘出现在相同的位置,而如果调整不正确,则某些边缘将迟到,某些边缘将提前取决于数据流中“1”和“0”的历史记录。 这是所谓的码间干扰的影响。 控制机构包括用于识别出现用于触发均衡器的调整的数据波形的最近历史中的“1”和“0”的模式的电路。
    • 2. 发明申请
    • Equalization circuit
    • 均衡电路
    • US20070002942A1
    • 2007-01-04
    • US11367660
    • 2006-03-03
    • Richard SimpsonRuediger Kuhn
    • Richard SimpsonRuediger Kuhn
    • H03H7/30H04B1/10
    • H04L7/033H04B3/06H04L25/03031H04L25/03885H04L2025/03681
    • An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether the edges between bits in the data waveform are early or late. Adjusting the equalization causes edges to appear in the same place, whereas if the adjustment is incorrect certain edges will be late and certain edges will be early depending on the history of “1”s and “0”s in the data stream. This is an effect of so-called intersymbol interference. The control mechanism includes circuits for recognizing patterns of “1”s and “0”s in the recent history of the data waveform whose occurrence is used to trigger the adjustment of the equalizer.
    • 特别是允许传输线进行低通滤波的均衡电路包括根据数据波形中的位之间的边缘是早还是晚的控制的补偿均衡器。 调整均衡会使边缘出现在相同的位置,而如果调整不正确,则某些边缘将迟到,某些边缘将提前取决于数据流中“1”和“0”的历史记录。 这是所谓的码间干扰的影响。 控制机构包括用于识别出现用于触发均衡器的调整的数据波形的最近历史中的“1”和“0”的模式的电路。
    • 3. 发明申请
    • Surgical Apparatus Including Surgical Buttress
    • 手术器械包括手术支架
    • US20120145767A1
    • 2012-06-14
    • US12964916
    • 2010-12-10
    • Sachin ShahRichard Simpson
    • Sachin ShahRichard Simpson
    • A61B17/068A61B17/32
    • A61B17/07207A61B17/07292A61B2017/00477A61B2017/00951A61B2017/07214
    • A surgical buttress for use with a surgical stapling apparatus having a first jaw in the form of an anvil assembly and a second jaw configured to selectively receive a staple cartridge assembly. The surgical buttress includes a first body portion and a second body portion. The first body portion substantially overlies a portion of a plurality of fastener slots of the staple cartridge assembly. The staple cartridge assembly is removably operably couplable to the second jaw of the surgical stapling apparatus. The second body portion extends from the first body portion and is configured and dimensioned to be removably positioned to substantially overlie a portion of a plurality of fastener pockets of the anvil assembly of the surgical stapling apparatus when the staple cartridge assembly is operably coupled to the second jaw of the surgical stapling apparatus.
    • 一种与外科缝合装置一起使用的手术支撑件,其具有砧座组件形式的第一钳口和被配置为选择性地容纳钉仓组件的第二钳口。 手术支撑体包括第一主体部分和第二主体部分。 第一主体部分基本上覆盖在钉仓组件的多个紧固件槽的一部分上。 钉仓组件可移除地可操作地联接到外科缝合装置的第二钳口。 第二主体部分从第一主体部分延伸并且被构造和尺寸设计成可拆卸地定位成基本覆盖在外科缝合装置的砧座组件的多个紧固件凹部的一部分上,当钉仓组件可操作地联接到第二主体部分 手术吻合装置的颚。
    • 4. 发明授权
    • Data transmission
    • 数据传输
    • US07236552B2
    • 2007-06-26
    • US10624262
    • 2003-07-22
    • Iain RobertsonRichard SimpsonMichael Harwood
    • Iain RobertsonRichard SimpsonMichael Harwood
    • H04L7/00
    • H04L7/0337H04L7/0025H04L25/14
    • A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.
    • 公开了并行接收多个串行数据流的电路。 从每个数据流恢复一个位时钟,有一个数据位用于时钟信号的正向和负向的ach转换。 比较时钟的相位并将其调整180度,使得所有位的正向沿都彼此接近。 每个流的位在字时钟的控制下组装成单词。 在一个实施例中,作为整体的位时钟集合导出公共字时钟。 在另一个实施例中,每个流被提供有其自己的字时钟,其对准彼此接近的相应位时钟的正边沿。
    • 8. 发明授权
    • Floating point exponent compare using repeated two bit compare cell
    • 使用重复的两位比较单元进行浮点指数比较
    • US5630160A
    • 1997-05-13
    • US400709
    • 1995-03-08
    • Richard SimpsonErick Oakland
    • Richard SimpsonErick Oakland
    • G06F7/02G06F7/00
    • G06F7/026G06F7/483
    • A magnitude comparator employs plural layers of repeated circuits which are scalable to any size. The magnitude comparator indicates whether two multibit inputs are equal, and if not equal indicates if a first multibit input is greater than a second multibit input. A single bit comparator circuit receives a corresponding bit of the two multibit inputs. Each single bit comparator generates an A=B output equal to the exclusive NOR of the two inputs and an A>B output equal to the first input. The magnitude comparator includes at least one two bit comparator circuit disposed in at least one layer. Each two bit comparator circuit includes an A[0]=B[0] input, an A[0]>B[0] input, an A[1]=B[1] input and an A[1]>B[1] input. Each two bit comparator circuit generates an A=B output of an AND of signals received at the A[0]=B[0] and A[1]=B[1] inputs. Each two bit comparator circuit generates an A>B output equal to the A[1]>B[1] input if the A[0]=B[0] input is "1" and equal to the A[0]>B[0] input if the A[0]=B[0] input is "0".
    • 幅度比较器采用可以任意尺寸缩放的多层重复电路。 幅度比较器指示两个多位输入是否相等,如果不相等则指示第一个多位输入是否大于第二个多位输入。 单位比较器电路接收两个多位输入的相应位。 每个单比特比较器产生等于两个输入的异或的A = B输出和等于第一个输入的A> B输出。 幅度比较器包括设置在至少一层中的至少一个二位比较器电路。 每个比特比较电路包括A [0] = B [0]输入,A [0]> B [0]输入,A [1] = B [1]输入和A [1]> B [ 1]输入。 每个2比特比较电路产生A [B]输入,A = B输出在A [0] = B [0]和A [1] = B [1]输入端接收的信号。 如果A [0] = B [0]输入为“1”,并且等于A [0]> B,则每两位比较电路产生等于A [1]> B [1]输入的A> B输出 如果A [0] = B [0]输入为“0”,则输入[0]。
    • 9. 发明授权
    • Adjustable water jet device
    • 可调式喷水装置
    • US08366016B2
    • 2013-02-05
    • US12909992
    • 2010-10-22
    • Richard Simpson
    • Richard Simpson
    • B05B17/08
    • B05B1/14B05B1/3026
    • An adjustable water jet device so as to continuously regulate the velocity of water exiting the device without interrupting the water flow, the water jet device including a nozzle body, rotatable nozzle seat, a flow control plate, an inlet, and a nozzle eyeball configured to direct the water supply, and a water supply system including the adjustable water jet device, a plate for accommodating the water jet device in a pool deck or pool wall, and a cover that is mounted flush with the pool deck or pool wall.
    • 一种可调节的喷水装置,以便连续地调节离开装置的水的速度而不中断水流,该喷水装置包括喷嘴体,可旋转的喷嘴座,流量控制板,入口和喷嘴眼球,其配置成 引导供水,以及包括可调节水喷射装置的供水系统,用于在水池甲板或池壁中容纳喷水装置的板以及与池甲板或池壁齐平地安装的盖。