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    • 10. 发明申请
    • Digital phase-locked loop
    • 数字锁相环
    • US20050265505A1
    • 2005-12-01
    • US10856447
    • 2004-05-28
    • Dale NelsonParag Parikh
    • Dale NelsonParag Parikh
    • H03D3/24H03L7/089H03L7/099H03L7/18
    • H03L7/089H03L7/0995H03L7/0997H03L7/18H03L2207/50
    • A phase-locked loop includes a variable frequency generator, a comparator and a counter. The variable frequency generator is configurable for generating an output signal having a frequency which varies based at least in part on at least first and second control signals presented thereto. The comparator is configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator. The comparator generates a difference signal representative of a difference between a phase and/or a frequency of the first and second signals, the difference signal comprising the first control signal. The counter is configurable for generating an output count based at least in part on the difference signal from the comparator. The output count is a digital representation of the difference signal, the output count comprising the second control signal. The frequency of the output signal from the variable frequency generator is determined as a function of the difference signal and the output count.
    • 锁相环包括可变频率发生器,比较器和计数器。 可变频率发生器可配置用于产生具有至少部分地基于呈现给其的至少第一和第二控制信号而变化的频率的输出信号。 比较器可配置为接收第一信号和第二信号,第一信号是呈现给锁相环的输入信号,第二信号代表来自可变频率发生器的输出信号。 比较器产生表示第一和第二信号的相位和/或频率之间的差的差分信号,差分信号包括第一控制信号。 计数器可配置用于至少部分地基于来自比较器的差分信号来产生输出计数。 输出计数是差分信号的数字表示,输出计数包括第二控制信号。 来自可变频率发生器的输出信号的频率被确定为差分信号和输出计数的函数。