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1. 发明授权

US06201283B1 Field effect transistor with double sided airbridge 失效
标题翻译：具双面气桥的场效应晶体管
公开(公告)号：US06201283B1
公开(公告)日：2001-03-13
申请号：US09391339
申请日：1999-09-08
申请人： Richard Lai , Yaochung Chen , Huan-Chun Yen , James C. K. Lau
发明人： Richard Lai , Yaochung Chen , Huan-Chun Yen , James C. K. Lau
IPC分类号： H01L2976
CPC分类号： H01L23/4821 , H01L29/42316 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A field effect transistor with a double sided airbridge comprises a substrate containing a conductive region and source, drain and gate electrodes disposed on the substrate. The gate electrode has a finger portion with a first end secured to the substrate between the source and drain electrodes and a second end, and a double sided airbridge portion flaring outwardly from the second end and having opposed first and second extremities. A first gate pad is disposed on said substrate outwardly from the source electrode and is connected to the first extremity. A second gate pad is disposed on said substrate outwardly from the drain electrodes and is connected to the second extremity. The gate pads serve to support the airbridge gate finger so as to reduce stress on the gate finger. The first and second gate pads receive and transmit signals through the airbridge and to and from the gate finger.
摘要翻译：具有双面气桥的场效应晶体管包括含有导电区域的基板和设置在基板上的源极，漏极和栅电极。栅电极具有手指部分，其第一端固定在源极和漏极之间的衬底上，第二端和从第二端向外扩张并具有相对的第一和第二端的双面气桥部分。第一栅极焊盘从源电极向外设置在所述衬底上并连接到第一末端。第二栅极焊盘从漏电极向外设置在所述衬底上，并连接到第二末端。闸板用于支撑空中桥闸手指，以减轻闸手指的压力。第一和第二栅极焊盘通过空中桥梁接收和传送信号，并且与门指接收和传送信号。

2. 发明授权

US06383826B1 Method for determining etch depth 失效
标题翻译：确定蚀刻深度的方法
公开(公告)号：US06383826B1
公开(公告)日：2002-05-07
申请号：US09691636
申请日：2000-10-18
申请人： Michael E. Barsky , Richard Lai , Ronald W. Grundbacher , Rosie M. Dia , Yaochung Chen
发明人： Michael E. Barsky , Richard Lai , Ronald W. Grundbacher , Rosie M. Dia , Yaochung Chen
IPC分类号： H01L2166
CPC分类号： H01L22/26 , H01L22/12
摘要： A method for determining the etch depth of a gate recess (26) in an InP based FET device (10). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.
摘要翻译：一种用于确定基于InP的FET器件（10）中的栅极凹槽（26）的蚀刻深度的方法。在蚀刻过程中监测源极 - 漏极，电流 - 电压（I-V）关系。当蚀刻深度增加时，在I-V关系的线性部分中形成扭结。当扭结电流达到所需值时，停止蚀刻。扭结电流是蚀刻深度的强函数，因此刻蚀深度的差异很小。通过控制蚀刻深度，可以可重复地控制和优化晶体管的特性。

3. 发明授权

US06551905B1 Wafer adhesive for semiconductor dry etch applications 有权
标题翻译：用于半导体干蚀刻应用的晶片粘合剂
公开(公告)号：US06551905B1
公开(公告)日：2003-04-22
申请号：US09693716
申请日：2000-10-20
申请人： Michael E. Barsky , Harvey N. Rogers , Vladimir Medvedev , Yaochung Chen , Richard Lai
发明人： Michael E. Barsky , Harvey N. Rogers , Vladimir Medvedev , Yaochung Chen , Richard Lai
IPC分类号： H01L2130
CPC分类号： H01L21/6835 , H01L21/76898 , H01L23/481 , H01L2221/68318 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A method is provided for backside processing a semiconductor wafer (10) including applying a polymer based protective coating (16) on the wafer, depositing a barrier layer of ceramic (18) on the protective coating, and coating the ceramic layer with a thermoplastic based adhesive (20). Thereafter, the wafer (10) is bonded to a perforated substrate (22) and then lapped and polished to a desired thickness and patterned with an etch mask. A high temperature plasma etching process is then used to etch via holes in the wafer (10). After etching and subsequent backside processing, the adhesive layer (20) is dissolved in acetone to separate the wafer (10) from the substrate (22). The protective coating (16) is then dissolved with a solvent to separate the ceramic layer (18) from the finished wafer (10).
摘要翻译：提供了一种用于背面处理半导体晶片（10）的方法，包括在晶片上施加基于聚合物的保护涂层（16），在保护涂层上沉积陶瓷（18）的阻挡层，并用基于热塑性的涂层粘合剂（20）。此后，将晶片（10）接合到多孔基材（22）上，然后研磨并抛光至所需厚度并用蚀刻掩模图案化。然后使用高温等离子体蚀刻工艺来蚀刻晶片（10）中的通孔。在蚀刻和随后的背面处理之后，将粘合剂层（20）溶解在丙酮中以将晶片（10）与基板（22）分离。然后用溶剂溶解保护涂层（16）以将陶瓷层（18）与成品晶片（10）分离。

4. 发明授权

US06764573B2 Wafer thinning techniques 有权
标题翻译：晶圆薄化技术
公开(公告)号：US06764573B2
公开(公告)日：2004-07-20
申请号：US09977158
申请日：2001-10-11
申请人： Richard Lai , Harvey N. Rogers , Yaochung Chen , Michael E. Barsky
发明人： Richard Lai , Harvey N. Rogers , Yaochung Chen , Michael E. Barsky
IPC分类号： B08B302
CPC分类号： H01L21/30612 , H01L21/302 , H01L21/67086 , H01L21/67346
摘要： Apparatuses (10, 100), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses (10, 100) include a fixture (12, 102) having a plurality of horizontal receptacles (14, 16, 18, 20, 104, 106, 108, 110) for receiving the semiconductor wafers (W). The loaded fixtures (12, 102) are then immersed into an etchant solution (36, 146) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution (36, 146) is preferably heated to about 40° C.-50° C. and constantly stirred with a magnetic stirring bar (48, 158). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution (36, 146). The apparatuses (10, 100) are capable of simultaneously thinning several semiconductor wafers (V) down to a final thickness of about 25 &mgr;m.
摘要翻译：描述了使用非结晶和均匀蚀刻工艺的装置（10,100）及其使用方法，用于同时薄化多个半导体晶片（W）的背面。装置（10,100）包括具有用于接收半导体晶片（W）的多个水平插座（14,16,18,20,104,106,108,110）的固定装置（12,102）。然后将装载的固定装置（12,102）浸入能够从半导体晶片（W）的背面各向同性地去除半导体材料层的蚀刻剂溶液（36,146）中。蚀刻剂溶液（36,146）优选加热至约40℃-50℃，并与磁力搅拌棒（48,158）持续搅拌。一旦经过足够的时间，就从蚀刻剂溶液（36,146）中除去变薄的半导体晶片（W）。装置（10,100）能够同时使多个半导体晶片（V）变薄至约25μm的最终厚度。

5. 发明授权

US06452221B1 Enhancement mode device 有权
标题翻译：增强模式设备
公开(公告)号：US06452221B1
公开(公告)日：2002-09-17
申请号：US09668120
申请日：2000-09-21
申请人： Richard Lai , Ronald W. Grundbacher , Yaochung Chen , Michael E. Barsky
发明人： Richard Lai , Ronald W. Grundbacher , Yaochung Chen , Michael E. Barsky
IPC分类号： H01L31072
CPC分类号： H01L29/7787
摘要： An enhancement mode FET device (10) that employs a strained N-doped InAlAs charge shield layer (22) disposed on an intrinsic InAlAs barrier layer (20). A gate metal electrode (38) of the FET device (10) is controllably diffused through a recess (36) into the shield layer (22) to the barrier layer (20). The resulting enhancement mode device (10) provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects through charge shielding by the shield layer (22) in the regions between the recess edge and the gate metal. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.
摘要翻译：一种使用设置在本征InAlAs势垒层（20）上的应变N掺杂InAlAs电荷屏蔽层（22）的增强型FET器件（10）。 FET器件（10）的栅极金属电极（38）通过凹部（36）被可控地扩散到屏蔽层（22）中至阻挡层（20）。所产生的增强模式器件（10）提供具有高势垒高度的优异的肖特基势垒，其通过在凹口边缘和栅极金属之间的区域中的屏蔽层（22）的电荷屏蔽来抑制不期望的表面消耗效应。通过使表面对加工条件和长期运行效果较不敏感，最小化表面耗尽效应使器件更加坚固。

6. 发明授权

US06524899B1 Process for forming a large area, high gate current HEMT diode 有权
标题翻译：用于形成大面积，高栅极电流HEMT二极管的工艺
公开(公告)号：US06524899B1
公开(公告)日：2003-02-25
申请号：US09667360
申请日：2000-09-21
申请人： Ronald W. Grundbacher , Richard Lai , Mark Kintis , Michael E. Barsky , Roger S. Tsai
发明人： Ronald W. Grundbacher , Richard Lai , Mark Kintis , Michael E. Barsky , Roger S. Tsai
IPC分类号： H01L21338
CPC分类号： H01L29/66143 , H01L21/30612 , H01L29/66462
摘要： A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.
摘要翻译：使用柠檬酸蚀刻剂制造HEMT IC的方法。为了通过单个蚀刻步骤形成不同尺寸的浇口，使用柠檬酸蚀刻剂，其包括柠檬酸钾，柠檬酸和过氧化氢。首先用光致抗蚀剂旋转晶片，然后通过光学光刻将其形成图案。将晶片浸入蚀刻剂中以蚀刻暴露的半导体材料。将金属电极蒸发到晶片上，并用溶剂除去剩余的光致抗蚀剂。

7. 发明申请

US20050026571A1 Asymmetric, optimized common-source bi-directional amplifier 有权
标题翻译：不对称，优化的公共源双向放大器
公开(公告)号：US20050026571A1
公开(公告)日：2005-02-03
申请号：US10632683
申请日：2003-08-01
申请人： Jeffrey Yang , Matt Nishimoto , Yun-Ho Chung , Michael Battung , Richard Lai
发明人： Jeffrey Yang , Matt Nishimoto , Yun-Ho Chung , Michael Battung , Richard Lai
IPC分类号： H03F3/193 , H03F3/62 , H04B1/18 , H04B1/40 , H04B1/44 , H04B1/38
CPC分类号： H03F1/56 , H03F3/193 , H03F3/62 , H03F2200/222 , H03F2200/372 , H03F2200/387 , H03F2200/451 , H04B1/44
摘要： A common source, bi-directional microwave amplifier is described. More particularly, the present invention is a microwave, common source, bi-directional amplifier that includes a first amplification path and a second amplification path wherein the signal directional flow is controlled through the selective biasing of the first amplification path and the second amplification path. Each amplification path is designed to optimize desired performance. For signal flow through the first amplification path, the first amplification path is biased-on and the second path is biased-off. For signal flow through the second amplification path, the second amplification path is biased-on and the first path is biased-off.
摘要翻译：描述了一种常见的源双向微波放大器。更具体地，本发明是一种微波公共源双向放大器，其包括第一放大路径和第二放大路径，其中通过第一放大路径和第二放大路径的选择性偏置来控制信号定向流。每个放大路径被设计为优化所需的性能。对于通过第一放大路径的信号流，第一放大路径被偏置，并且第二路径被偏置。对于通过第二放大路径的信号流，第二放大路径被偏置，并且第一路径被偏置。

8. 发明申请

US20080111157A1 High electron mobility transistor semiconductor device and fabrication method thereof 有权
标题翻译：高电子迁移率晶体管半导体器件及其制造方法
公开(公告)号：US20080111157A1
公开(公告)日：2008-05-15
申请号：US11598817
申请日：2006-11-14
申请人： Linh Dang , Wayne Yoshida , Xiaobing Mei , Jennifer Wang , Po-Hsin Liu , Jane Lee , Weidong Liu , Michael Barsky , Richard Lai
发明人： Linh Dang , Wayne Yoshida , Xiaobing Mei , Jennifer Wang , Po-Hsin Liu , Jane Lee , Weidong Liu , Michael Barsky , Richard Lai
IPC分类号： H01L29/778 , H01L21/28
CPC分类号： H01L29/66462 , H01L21/28587 , H01L21/32139 , H01L29/42316
摘要： In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).
摘要翻译：在半导体衬底（100）上形成半导体器件的方法中，在半导体衬底上沉积光致抗蚀剂层（102）通过电子束光刻在光致抗蚀剂层（102）中形成窗口（106）在光致抗蚀剂层（102）和窗口（106）中沉积共形层（108）; 并且基本上所有的保形层（108）从光致抗蚀剂层（102）和窗口的底部部分选择性地移除，以在窗口（106）中形成电介质侧壁（110）。

9. 发明授权

US5129666A Aluminum alloy bicycle frame 失效
标题翻译：铝合金自行车架
公开(公告)号：US5129666A
公开(公告)日：1992-07-14
申请号：US639295
申请日：1991-01-10
申请人： Richard Lai
发明人： Richard Lai
IPC分类号： B62K19/22 , B62K19/24
CPC分类号： B62K19/22 , B62K19/24 , Y10T403/472 , Y10T403/473
摘要： An aluminum alloy bicycle frame includes a set of tubes and a set of joint members for connecting the tubes, each of the joint members having a tubular joining portion. Each of the tubes has an externally threaded end provided with adhesive glue, and the tubular joining portion of each of the joint members has a threaded inner face provided with adhesive glue. The externally threaded ends of the tubes are respectively screwed into and adhered to the tubular joining portions of the joint members. This frame has strong joints which are clean and smooth in appearance, without requiring a high degree skill or unusually expensive materials.
摘要翻译：一种铝合金自行车车架包括一组管和一组用于连接管的接头构件，每个接头构件具有管状接合部分。每个管具有设置有胶粘剂的外螺纹端，并且每个接头构件的管状接合部分具有带有胶粘剂的螺纹内表面。管的外螺纹端分别旋入并粘接到接头构件的管状接合部分。该框架具有坚固的接头，其外观干净平滑，无需高度的技术或异常昂贵的材料。

10. 发明授权

US07947320B2 Production of multi-grain, whole-grain, soft and crunchy sheeted snacks 有权
标题翻译：生产多粒，全谷物，软脆松脆的小吃
公开(公告)号：US07947320B2
公开(公告)日：2011-05-24
申请号：US12370294
申请日：2009-02-12
申请人： Pierre Faa , Richard Lai
发明人： Pierre Faa , Richard Lai
IPC分类号： A23L1/10
CPC分类号： A23L7/126 , A23L7/115 , A23L7/117 , A23L29/212 , Y10S426/808
摘要： The present invention discloses a method for making a multi-grain, whole grain baked snack food product with a soft, crunchy texture similar to a cracker. Ingredient formula ranges have been determined that maximize the amount and number of nutritious whole grains present in the snack food, while still keeping the texture soft and crunchy, and the color and flavor acceptable. The ingredients are combined with water to make a dough, which is then sheeted and cut into pieces. The pieces are baked to produce a multi-grain, whole grain baked snack food.
摘要翻译：本发明公开了一种制作具有类似于裂化器的柔软，脆脆质地的多颗粒全粒面烘烤小吃食品的方法。已经确定成分配方范围，使零食中存在的营养全谷物的数量和数量最大化，同时仍保持质地柔软和脆脆，并且颜色和风味可接受。将成分与水混合以制成面团，然后将其切片并切成块。这些碎片被烘烤以产生多粒，全谷物烘烤的零食。

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