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1. 发明授权

US08504884B2 Threshold voltage techniques for detecting an imminent read failure in a memory array 有权
标题翻译：用于检测存储器阵列中即将发生的读取故障的阈值电压技术
公开(公告)号：US08504884B2
公开(公告)日：2013-08-06
申请号：US12608405
申请日：2009-10-29
申请人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
发明人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
IPC分类号： G11C29/00
CPC分类号： G11C29/50004 , G11C16/26 , G11C29/42 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
摘要翻译：用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。

2. 发明授权

US08095836B2 Time-based techniques for detecting an imminent read failure in a memory array 有权
标题翻译：用于检测存储器阵列中即将发生的读取故障的基于时间的技术
公开(公告)号：US08095836B2
公开(公告)日：2012-01-10
申请号：US12608476
申请日：2009-10-29
申请人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew
发明人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew
IPC分类号： G11C29/42 , G11C29/50
CPC分类号： G06F11/1008 , G06F11/004 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.
摘要翻译：一种用于检测存储器阵列中即将发生的读取故障的技术包括确定在阵列完整性检查期间不显示读取的不可校正纠错码（ECC）的存储器阵列的第一事件计数。在这种情况下，第一事件计数对应于当存储器阵列的阵列完整性检查最初失败时执行的ECC校正的初始数量。该技术还包括当在随后的阵列完整性检查期间存储器阵列不呈现不可校正的ECC读取时确定存储器阵列的当前计数。在这种情况下，当前计数对应于随后的阵列完整性检查期间所需的纠错码（ECC）修正的随后数量。当当前计数超过第一事件计数预定量时，提供存储器阵列即将发生读取故障的指示。

3. 发明申请

US20110107161A1 THRESHOLD VOLTAGE TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY 有权
标题翻译：用于检测存储器阵列中的立即读取故障的阈值电压技术
公开(公告)号：US20110107161A1
公开(公告)日：2011-05-05
申请号：US12608405
申请日：2009-10-29
申请人： Richard Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
发明人： Richard Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/50004 , G11C16/26 , G11C29/42 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
摘要翻译：用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。

4. 发明申请

US20110107160A1 TIME-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY 有权
标题翻译：用于检测存储器阵列中的立即读取故障的基于时间的技术
公开(公告)号：US20110107160A1
公开(公告)日：2011-05-05
申请号：US12608476
申请日：2009-10-29
申请人： Richard Eguchi , Thomas S. Harp , Thomas Jew
发明人： Richard Eguchi , Thomas S. Harp , Thomas Jew
IPC分类号： G11C29/04 , G06F11/00 , G06F11/22
CPC分类号： G06F11/1008 , G06F11/004 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.
摘要翻译：一种用于检测存储器阵列中即将发生的读取故障的技术包括确定在阵列完整性检查期间不显示读取的不可校正纠错码（ECC）的存储器阵列的第一事件计数。在这种情况下，第一事件计数对应于当存储器阵列的阵列完整性检查最初失败时执行的ECC校正的初始数量。该技术还包括当在随后的阵列完整性检查期间存储器阵列不呈现不可校正的ECC读取时确定存储器阵列的当前计数。在这种情况下，当前计数对应于随后的阵列完整性检查期间所需的纠错码（ECC）修正的随后数量。当当前计数超过第一事件计数预定量时，提供存储器阵列即将发生读取故障的指示。

5. 发明授权

US07599236B2 In-circuit Vt distribution bit counter for non-volatile memory devices 有权
标题翻译：用于非易失性存储器件的在线Vt分配位计数器
公开(公告)号：US07599236B2
公开(公告)日：2009-10-06
申请号：US11448225
申请日：2006-06-07
申请人： Richard K. Eguchi , Larry J. Grieve , Thomas Jew
发明人： Richard K. Eguchi , Larry J. Grieve , Thomas Jew
IPC分类号： G11C29/00
CPC分类号： G11C8/12 , G11C16/04 , G11C29/38 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C29/56008
摘要： Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of 0's or 1's for a specified voltage. As the range of addresses are scanned across a range of voltages, the instances of the count value being counted is accumulated by the bit counter. Automated Tester Equipment (ATE) reads the accumulated count value for each tested voltage.
摘要翻译：非易失性存储器模块中的集成测试组件和测试算法在模块验证过程中提供更快的Vt（阈值电压）分布。存储器模块包括地址和电压扫描组件，以及用于存储指定电压的0或1的数量的位计数器。由于在一定范围的电压范围内扫描地址范围，所以计数的计数值的实例由位计数器累积。自动测试设备（ATE）读取每个测试电压的累计计数值。

6. 发明申请

US20070285986A1 In-circuit Vt distribution bit counter for non-volatile memory devices 有权
标题翻译：用于非易失性存储器件的在线Vt分配位计数器
公开(公告)号：US20070285986A1
公开(公告)日：2007-12-13
申请号：US11448225
申请日：2006-06-07
申请人： Richard K. Eguchi , Larry J. Grieve , Thomas Jew
发明人： Richard K. Eguchi , Larry J. Grieve , Thomas Jew
IPC分类号： G11C11/34
CPC分类号： G11C8/12 , G11C16/04 , G11C29/38 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C29/56008
摘要： Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of 0's or 1's for a specified voltage. As the range of addresses are scanned across a range of voltages, the instances of the count value being counted is accumulated by the bit counter. Automated Tester Equipment (ATE) reads the accumulated count value for each tested voltage.
摘要翻译：非易失性存储器模块中的集成测试组件和测试算法在模块验证过程中提供更快的Vt（阈值电压）分布。存储器模块包括地址和电压扫描组件，以及用于存储指定电压的0或1的数量的位计数器。由于在一定范围的电压范围内扫描地址范围，所以计数的计数值的实例由位计数器累积。自动测试设备（ATE）读取每个测试电压的累计计数值。

7. 发明授权

US07668018B2 Electronic device including a nonvolatile memory array and methods of using the same 有权
标题翻译：包括非易失性存储器阵列的电子设备及其使用方法
公开(公告)号：US07668018B2
公开(公告)日：2010-02-23
申请号：US11695722
申请日：2007-04-03
申请人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Thomas Jew
发明人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Thomas Jew
IPC分类号： G11C16/04
CPC分类号： G11C16/349
摘要： An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.
摘要翻译：电子设备可以包括第一存储器单元和第二存储单元。第一存储单元可以包括第一源，而第二存储单元可以包括第二源。第一存储器单元和第二存储器单元可以位于存储器阵列的相同扇区内。在一个实施例中，擦除电子设备可以包括在禁止第二存储器单元的擦除的同时擦除第一存储器单元。第三存储器单元可具有第三源并位于另一扇区内。在另一个实施例中，禁止第一存储器单元的擦除可以包括将第一源和第三源放置在相同的电位。在特定实施例中，第一源可以与第二源电绝缘。

8. 发明申请

US20070220388A1 Apparatus and method for adjusting an operating parameter of an integrated circuit 有权
标题翻译：用于调整集成电路的工作参数的装置和方法
公开(公告)号：US20070220388A1
公开(公告)日：2007-09-20
申请号：US11366286
申请日：2006-03-02
申请人： Qadeer Quereshi , James Burnett , Jack Higman , Thomas Jew
发明人： Qadeer Quereshi , James Burnett , Jack Higman , Thomas Jew
IPC分类号： G01R31/28
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.
摘要翻译：一种用于调整具有存储器和逻辑的集成电路的操作参数的方法，其中所述逻辑包括定时电路，包括访问所述存储器，确定所述存储器访问相对于所述定时电路的速度的相对速度，以及选择性地根据相对速度调整运行参数。在一个实施例中，集成电路可以包括环形振荡器，具有耦合到环形振荡器的输出的时钟输入的移位寄存器以及耦合到移位寄存器的输出的比较逻辑。响应于启动对存储器的存储器访问而响应于完成存储器访问而禁用移位寄存器。比较逻辑提供表示存储器的相对速度的相对速度指示符。

9. 发明授权

US07269090B2 Memory access with consecutive addresses corresponding to different rows 有权
标题翻译：内存访问与不同行对应的连续地址
公开(公告)号：US07269090B2
公开(公告)日：2007-09-11
申请号：US09772830
申请日：2001-01-30
申请人： Frank K. Baker, Jr. , James D. Burnett , Thomas Jew
发明人： Frank K. Baker, Jr. , James D. Burnett , Thomas Jew
IPC分类号： G06F7/00 , G06F8/00
CPC分类号： G11C16/3427 , G06F12/0607 , G11C16/08 , G11C16/3418
摘要： A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.
摘要翻译：存储器系统（200）具有排列成多行和多列的可寻址存储元件（210）的阵列，以及耦合到可寻址存储元件（210）阵列的解码电路（220,230）。解码电路（220,230）响应于对第一地址的解码而访问多行中的第一行的第一存储元件，并且响应于解码与第一地址连续的第二地址，访问第二地址多行的第二行的存储元件。多行中的第二行与多行中的第一行不同。通过实现其中连续地址对应于不同行的存储元件的存储器系统，可以将沿着单个行的读取干扰应力最小化。

10. 发明授权

US6101130A Semiconductor device memory cell and method for selectively erasing the same 失效
标题翻译：半导体器件存储单元及其选择性擦除方法
公开(公告)号：US6101130A
公开(公告)日：2000-08-08
申请号：US342470
申请日：1999-06-29
申请人： Frank Kelsey Baker , Juan Buxo , Danny Pak-Chum Shum , Thomas Jew
发明人： Frank Kelsey Baker , Juan Buxo , Danny Pak-Chum Shum , Thomas Jew
IPC分类号： G11C16/02 , G11C16/04 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0416 , G11C16/14
摘要： An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).
摘要翻译：一种电可擦除可编程只读存储器（EEPROM）阵列（30），其包括存储器单元的行和列。字线（WL0和WL1）基本上彼此平行并且在第一方向上延伸。排列位线（BL0-B13）和源极线（SL0和SL1）基本上彼此平行并且在垂直于第一方向的第二方向上延伸。 EEPROM阵列内的至少两个存储单元（31和36）的源极线（SL0）和源极区域通过第一源局部互连（LI1）电连接。第一源局部互连（LI1）具有基本上在第一方向上延伸的长度，并电连接位于EEPROM阵列（30）内的一些但不是全部的存储器单元。

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