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1. 发明授权

US08504884B2 Threshold voltage techniques for detecting an imminent read failure in a memory array 有权
标题翻译：用于检测存储器阵列中即将发生的读取故障的阈值电压技术
公开(公告)号：US08504884B2
公开(公告)日：2013-08-06
申请号：US12608405
申请日：2009-10-29
申请人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
发明人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
IPC分类号： G11C29/00
CPC分类号： G11C29/50004 , G11C16/26 , G11C29/42 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
摘要翻译：用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。

2. 发明授权

US08095836B2 Time-based techniques for detecting an imminent read failure in a memory array 有权
标题翻译：用于检测存储器阵列中即将发生的读取故障的基于时间的技术
公开(公告)号：US08095836B2
公开(公告)日：2012-01-10
申请号：US12608476
申请日：2009-10-29
申请人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew
发明人： Richard K. Eguchi , Thomas S. Harp , Thomas Jew
IPC分类号： G11C29/42 , G11C29/50
CPC分类号： G06F11/1008 , G06F11/004 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.
摘要翻译：一种用于检测存储器阵列中即将发生的读取故障的技术包括确定在阵列完整性检查期间不显示读取的不可校正纠错码（ECC）的存储器阵列的第一事件计数。在这种情况下，第一事件计数对应于当存储器阵列的阵列完整性检查最初失败时执行的ECC校正的初始数量。该技术还包括当在随后的阵列完整性检查期间存储器阵列不呈现不可校正的ECC读取时确定存储器阵列的当前计数。在这种情况下，当前计数对应于随后的阵列完整性检查期间所需的纠错码（ECC）修正的随后数量。当当前计数超过第一事件计数预定量时，提供存储器阵列即将发生读取故障的指示。

3. 发明申请

US20110107161A1 THRESHOLD VOLTAGE TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY 有权
标题翻译：用于检测存储器阵列中的立即读取故障的阈值电压技术
公开(公告)号：US20110107161A1
公开(公告)日：2011-05-05
申请号：US12608405
申请日：2009-10-29
申请人： Richard Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
发明人： Richard Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/50004 , G11C16/26 , G11C29/42 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
摘要翻译：用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。

4. 发明申请

US20110107160A1 TIME-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY 有权
标题翻译：用于检测存储器阵列中的立即读取故障的基于时间的技术
公开(公告)号：US20110107160A1
公开(公告)日：2011-05-05
申请号：US12608476
申请日：2009-10-29
申请人： Richard Eguchi , Thomas S. Harp , Thomas Jew
发明人： Richard Eguchi , Thomas S. Harp , Thomas Jew
IPC分类号： G11C29/04 , G06F11/00 , G06F11/22
CPC分类号： G06F11/1008 , G06F11/004 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.
摘要翻译：一种用于检测存储器阵列中即将发生的读取故障的技术包括确定在阵列完整性检查期间不显示读取的不可校正纠错码（ECC）的存储器阵列的第一事件计数。在这种情况下，第一事件计数对应于当存储器阵列的阵列完整性检查最初失败时执行的ECC校正的初始数量。该技术还包括当在随后的阵列完整性检查期间存储器阵列不呈现不可校正的ECC读取时确定存储器阵列的当前计数。在这种情况下，当前计数对应于随后的阵列完整性检查期间所需的纠错码（ECC）修正的随后数量。当当前计数超过第一事件计数预定量时，提供存储器阵列即将发生读取故障的指示。

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