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1. 发明授权

US07668018B2 Electronic device including a nonvolatile memory array and methods of using the same 有权
标题翻译：包括非易失性存储器阵列的电子设备及其使用方法
公开(公告)号：US07668018B2
公开(公告)日：2010-02-23
申请号：US11695722
申请日：2007-04-03
申请人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Thomas Jew
发明人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Thomas Jew
IPC分类号： G11C16/04
CPC分类号： G11C16/349
摘要： An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.
摘要翻译：电子设备可以包括第一存储器单元和第二存储单元。第一存储单元可以包括第一源，而第二存储单元可以包括第二源。第一存储器单元和第二存储器单元可以位于存储器阵列的相同扇区内。在一个实施例中，擦除电子设备可以包括在禁止第二存储器单元的擦除的同时擦除第一存储器单元。第三存储器单元可具有第三源并位于另一扇区内。在另一个实施例中，禁止第一存储器单元的擦除可以包括将第一源和第三源放置在相同的电位。在特定实施例中，第一源可以与第二源电绝缘。

2. 发明申请

US20080247255A1 ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS OF USING THE SAME 有权
标题翻译：包含非易失性存储器阵列的电子设备及其使用方法
公开(公告)号：US20080247255A1
公开(公告)日：2008-10-09
申请号：US11695722
申请日：2007-04-03
申请人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Thomas Jew
发明人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Thomas Jew
IPC分类号： G11C16/06 , G11C7/00 , G11C7/10
CPC分类号： G11C16/349
摘要： An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.
摘要翻译：电子设备可以包括第一存储器单元和第二存储单元。第一存储单元可以包括第一源，而第二存储单元可以包括第二源。第一存储器单元和第二存储器单元可以位于存储器阵列的相同扇区内。在一个实施例中，擦除电子设备可以包括擦除第一存储器单元，同时抑制第二存储单元的擦除。第三存储器单元可具有第三源并位于另一扇区内。在另一个实施例中，禁止第一存储器单元的擦除可以包括将第一源和第三源放置在相同的电位。在特定实施例中，第一源可以与第二源电绝缘。

3. 发明申请

US20080043525A1 Bit cell reference device and methods thereof 有权
标题翻译：比特单元参考装置及其方法
公开(公告)号：US20080043525A1
公开(公告)日：2008-02-21
申请号：US11435944
申请日：2006-05-17
申请人： Ronald J. Syzdek , Gowrishankar L. Chindalore
发明人： Ronald J. Syzdek , Gowrishankar L. Chindalore
IPC分类号： G11C16/06 , G11C16/04 , G11C7/04 , G11C11/34
CPC分类号： G11C7/062 , G11C7/14 , G11C16/28 , G11C16/3427 , G11C2207/063
摘要： A memory device is disclosed. A reference device of the memory includes a trimmable current source and a fixed current source. Currents provided by each source are summed to provide a reference current to a sense amplifier. The sense amplifier senses the state of a bit cell by comparing a current from the bit cell, representative of a logic value, to the reference current. By basing the reference current on both a fixed and a trimmable current source, the reference device can be trimmed to compensate for process and operating characteristics of the device, while maintaining a minimum reference current in the event of a disturb mechanism that results in loss of the current provided by the trimmable current source.
摘要翻译：公开了一种存储器件。存储器的参考装置包括可调整电流源和固定电流源。每个源提供的电流被相加以向读出放大器提供参考电流。感测放大器通过将来自代表逻辑值的位单元的电流与参考电流进行比较来感测比特单元的状态。通过将参考电流设置在固定电流源和可调整电流源上，可以对参考装置进行修整，以补偿器件的工艺和工作特性，同时在造成损失的干扰机制的情况下保持最小参考电流由可调电流源提供的电流。

4. 发明授权

US07649781B2 Bit cell reference device and methods thereof 有权
标题翻译：比特单元参考装置及其方法
公开(公告)号：US07649781B2
公开(公告)日：2010-01-19
申请号：US11435944
申请日：2006-05-17
申请人： Ronald J. Syzdek , Gowrishankar L. Chindalore
发明人： Ronald J. Syzdek , Gowrishankar L. Chindalore
IPC分类号： G11C16/06
CPC分类号： G11C7/062 , G11C7/14 , G11C16/28 , G11C16/3427 , G11C2207/063
摘要： A memory device is disclosed. A reference device of the memory includes a trimmable current source and a fixed current source. Currents provided by each source are summed to provide a reference current to a sense amplifier. The sense amplifier senses the state of a bit cell by comparing a current from the bit cell, representative of a logic value, to the reference current. By basing the reference current on both a fixed and a trimmable current source, the reference device can be trimmed to compensate for process and operating characteristics of the device, while maintaining a minimum reference current in the event of a disturb mechanism that results in loss of the current provided by the trimmable current source.
摘要翻译：公开了一种存储器件。存储器的参考装置包括可调整电流源和固定电流源。每个源提供的电流被相加以向读出放大器提供参考电流。感测放大器通过将来自代表逻辑值的位单元的电流与参考电流进行比较来感测比特单元的状态。通过将参考电流设置在固定电流源和可调整电流源上，可以对参考装置进行修整，以补偿器件的工艺和工作特性，同时在造成损失的干扰机制的情况下保持最小参考电流由可调电流源提供的电流。

5. 发明授权

US07259999B2 Non-volatile memory cell array for improved data retention and method of operating thereof 有权
标题翻译：用于改进数据保留的非易失性存储单元阵列及其操作方法
公开(公告)号：US07259999B2
公开(公告)日：2007-08-21
申请号：US11258745
申请日：2005-10-26
申请人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Paul A. Ingersoll , Peter J. Kuhn
发明人： Ronald J. Syzdek , Gowrishankar L. Chindalore , Paul A. Ingersoll , Peter J. Kuhn
IPC分类号： G11C7/10
CPC分类号： G11C16/16
摘要： A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an erased state. The method also includes programming a second plurality of non-volatile memory bit cells in the memory block during the erase procedure, such that the second plurality of non-volatile memory bit cells is a subset of the third plurality of non-volatile memory bit cells and upon completion of the erase procedure, the second plurality of non-volatile memory bit cells are at a programmed state.
摘要翻译：提供了一种方法，其包括在擦除过程期间擦除包括第三多个存储器位单元的存储器块中的第一多个非易失性存储器位单元，使得在擦除过程完成时，第一多个非易失性存储器位单元存储器位单元处于擦除状态。该方法还包括在擦除过程期间在存储器块中编程第二多个非易失性存储器位单元，使得第二多个非易失性存储器位单元是第三多个非易失性存储器位单元的子集并且在擦除过程完成时，第二多个非易失性存储器位单元处于编程状态。

6. 发明授权

US09685339B2 Scalable split gate memory cell array 有权
公开(公告)号：US09685339B2
公开(公告)日：2017-06-20
申请号：US13873917
申请日：2013-04-30
申请人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang , Ronald J. Syzdek
发明人： Jane A. Yater , Cheong Min Hong , Sung-Taeg Kang , Ronald J. Syzdek
IPC分类号： H01L27/115 , H01L21/28 , H01L29/423 , H01L27/11521
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42332
摘要： A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.

7. 发明授权

US09111629B2 Smart charge pump configuration for non-volatile memories 有权
标题翻译：智能电荷泵配置用于非易失性存储器
公开(公告)号：US09111629B2
公开(公告)日：2015-08-18
申请号：US13441335
申请日：2012-04-06
申请人： Jeffrey C. Cunningham , Karthik Ramanan , Ross S. Scouller , Ronald J. Syzdek
发明人： Jeffrey C. Cunningham , Karthik Ramanan , Ross S. Scouller , Ronald J. Syzdek
IPC分类号： G11C16/04 , G11C16/30 , G11C5/14 , G11C8/08 , G11C16/34
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/3454
摘要： A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.
摘要翻译：半导体存储器件包括非易失性存储器，存储器控制器和电荷泵系统。存储器控制器在执行第一编程周期之前为非易失性存储器的第一多个存储器单元的第一编程周期建立第一参数。电荷泵系统包括多个电荷泵并提供用于执行第一程序循环的第一编程脉冲。第一编程脉冲通过根据第一参数选择在第一编程周期期间启用多个电荷泵中的哪一个并在第一编程周期期间被禁用来提供。

8. 发明授权

US08971147B2 Control gate word line driver circuit for multigate memory 有权
标题翻译：用于多存储器的控制门字线驱动电路
公开(公告)号：US08971147B2
公开(公告)日：2015-03-03
申请号：US13663636
申请日：2012-10-30
申请人： Gilles Muller , Ronald J. Syzdek
发明人： Gilles Muller , Ronald J. Syzdek
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/26 , G11C16/30
摘要： A memory having an array of multi-gate memory cells and a word line driver circuit coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.
摘要翻译：具有多栅极存储器单元阵列的存储器和耦合到阵列的存储器单元的扇区的字线驱动器电路。在至少一种操作模式中，字线驱动器电路是可控制的，以将耦合到控制栅极字线驱动器的相关联的控制栅极字线放置在浮动状态下，在读取操作期间扇区是非线性的，选定部门。

9. 发明申请

US20130346680A1 EMULATED ELECTRICALLY ERASABLE MEMORY HAVING AN ADDRESS RAM FOR DATA STORED IN FLASH MEMORY 审中-公开
标题翻译：具有存储在闪存中的数据的地址RAM的模拟电可擦除存储器
公开(公告)号：US20130346680A1
公开(公告)日：2013-12-26
申请号：US13530169
申请日：2012-06-22
申请人： Ross S. Scouller , Frank K. Baker, JR. , Ronald J. Syzdek
发明人： Ross S. Scouller , Frank K. Baker, JR. , Ronald J. Syzdek
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7207
摘要： A memory system comprises a memory controller, an address RAM coupled to the memory controller, and a non-volatile memory coupled to the memory controller. The non-volatile memory has an address portion and a data portion. The address portion of the non-volatile memory provides data portion addresses and data portion addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory. The memory controller uses the data portion addresses, and locations of the data block addresses within the address RAM, to locate data blocks within the data portion of non-volatile memory
摘要翻译：存储器系统包括存储器控制器，耦合到存储器控制器的地址RAM以及耦合到存储器控制器的非易失性存储器。非易失性存储器具有地址部分和数据部分。非易失性存储器的地址部分向存储器控制器提供有效数据的数据部分地址和数据部分地址。存储器控制器加载数据部分地址并将它们存储在地址RAM中，在由有效数据的数据部分地址定义的地址到地址RAM中。存储器控制器使用数据部分地址和地址RAM内的数据块的位置来定位非易失性存储器的数据部分内的数据块。存储器控制器使用数据部分地址和地址RAM内的数据块地址的位置来定位非易失性存储器的数据部分内的数据块

10. 发明授权

US07742340B2 Read reference technique with current degradation protection 失效
标题翻译：阅读参考技术与当前的降解保护
公开(公告)号：US07742340B2
公开(公告)日：2010-06-22
申请号：US12048683
申请日：2008-03-14
申请人： Fuchen Mu , Marco A. Cabassi , Ronald J. Syzdek
发明人： Fuchen Mu , Marco A. Cabassi , Ronald J. Syzdek
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5642
摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.
摘要翻译：一组参考单元用于感测存储在存储器件的位单元中的数据值。响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。

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