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1. 发明授权

US07902599B2 Integrated circuit having long and short channel metal gate devices and method of manufacture 有权
标题翻译：具有长和短沟道金属栅极器件的集成电路及其制造方法
公开(公告)号：US07902599B2
公开(公告)日：2011-03-08
申请号：US12607710
申请日：2009-10-28
申请人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
发明人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
IPC分类号： H01L29/78
CPC分类号： H01L21/823456 , H01L21/28114 , H01L21/823468 , H01L29/4933 , H01L29/66545
摘要： Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the SC device, and is formed substantially from the same metal as is the LC metal gate.
摘要翻译：提供集成电路的实施例。在一个实施例中，集成电路包括衬底，短沟道（SC）器件和长沟道（LC）器件。短沟道器件包括覆盖衬底的第一部分的SC栅极绝缘体，覆盖SC栅极绝缘体的SC金属栅极，覆盖在金属栅极上的多晶硅层和形成在多晶硅层上的硅化物层。长沟道（LC）器件包括覆盖衬底的第二部分的LC栅极绝缘体和覆盖LC栅极绝缘体的LC金属栅极。蚀刻停止层覆盖在衬底的上表面上，并且层间电介质覆盖在蚀刻停止层的上表面上。 SC盖设置在层间电介质中，覆盖SC器件，并且基本上由与LC金属栅极相同的金属形成。

2. 发明授权

US07723192B2 Integrated circuit long and short channel metal gate devices and method of manufacture 有权
标题翻译：集成电路长短通道金属栅极器件及其制造方法
公开(公告)号：US07723192B2
公开(公告)日：2010-05-25
申请号：US12048414
申请日：2008-03-14
申请人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
发明人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/28114 , H01L21/823468 , H01L29/4933 , H01L29/66545
摘要： A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.
摘要翻译：提供了一种用于制造集成电路的方法，该集成电路包括短沟道（SC）器件和每个由层间电介质覆盖的长沟道（LC）器件。 SC器件具有SC栅极堆叠，LC器件最初具有虚拟栅极。在一个实施例中，该方法包括以下步骤：去除伪栅极以形成LC器件沟槽，以及在SC器件和LC器件上沉积金属栅极材料。金属栅极材料接触SC栅极堆叠并且基本上填充LC器件沟槽。

3. 发明授权

US08716828B2 Semiconductor device with isolation trench liner 有权
标题翻译：半导体器件带隔离沟槽衬垫
公开(公告)号：US08716828B2
公开(公告)日：2014-05-06
申请号：US13473175
申请日：2012-05-16
申请人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
发明人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
IPC分类号： H01L21/70
CPC分类号： H01L21/76232
摘要： A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.
摘要翻译：半导体器件包括其中限定有活性晶体管区域的半导体材料层，形成在与有源晶体管区域相邻的半导体材料中的隔离沟槽和衬在隔离沟槽上的沟槽衬垫，其中沟槽衬垫由材料形成，基本上禁止在其上形成高k材料，并且其中隔离沟槽和沟槽衬里一起形成衬里的沟槽。该器件在衬里沟槽中具有绝缘材料，并且高k栅极材料覆盖绝缘材料的至少一部分并且覆盖有源晶体管区域的至少一部分，使得沟槽衬垫将高k 栅极材料覆盖绝缘材料的至少一部分与覆盖有源晶体管区域的至少一部分的高k栅极材料。

4. 发明授权

US07998832B2 Semiconductor device with isolation trench liner, and related fabrication methods 有权
标题翻译：具有隔离沟槽衬垫的半导体器件及相关制造方法
公开(公告)号：US07998832B2
公开(公告)日：2011-08-16
申请号：US12199616
申请日：2008-08-27
申请人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
发明人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
IPC分类号： H01L29/00
CPC分类号： H01L21/76232
摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
摘要翻译：这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。然后用绝缘材料填充衬里的沟槽。此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

5. 发明授权

US08217472B2 Semiconductor device with isolation trench liner 有权
标题翻译：半导体器件带隔离沟槽衬垫
公开(公告)号：US08217472B2
公开(公告)日：2012-07-10
申请号：US13178362
申请日：2011-07-07
申请人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
发明人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
IPC分类号： H01L29/772
CPC分类号： H01L21/76232
摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
摘要翻译：这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。然后用绝缘材料填充衬里的沟槽。此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

6. 发明申请

US20100052094A1 SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER, AND RELATED FABRICATION METHODS 有权
标题翻译：具有隔离衬板的半导体器件及相关制造方法
公开(公告)号：US20100052094A1
公开(公告)日：2010-03-04
申请号：US12199616
申请日：2008-08-27
申请人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
发明人： Richard J. Carter , George J. Kluth , Michael J. Hargrove
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76232
摘要： A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.
摘要翻译：这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。然后用绝缘材料填充衬里的沟槽。此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

7. 发明授权

US06627504B1 Stacked double sidewall spacer oxide over nitride 失效
标题翻译：堆叠的双侧壁间隔氧化物在氮化物上
公开(公告)号：US06627504B1
公开(公告)日：2003-09-30
申请号：US09778114
申请日：2001-02-07
申请人： Jacques J. Bertrand , George J. Kluth
发明人： Jacques J. Bertrand , George J. Kluth
IPC分类号： H01L21336
CPC分类号： H01L29/66553 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by recessing the silicon nitride spacers and forming barrier spacers on top of the silicon nitride spacers. The barrier spacers prevent silicon migration and hence the formation of bridging silicide on the silicon nitride sidewall spacers.
摘要翻译：通过在氮化硅间隔物的顶部凹入氮化硅间隔物并形成阻挡隔离物来防止在栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接。阻挡间隔物防止硅迁移，从而在氮化硅侧壁间隔物上形成桥接硅化物。

8. 发明授权

US06872613B1 Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure 有权
标题翻译：用于形成具有不同功函数的金属以形成具有高k栅极电介质和相关结构的CMOS栅极的方法
公开(公告)号：US06872613B1
公开(公告)日：2005-03-29
申请号：US10654689
申请日：2003-09-04
申请人： Qi Xiang , Huicai Zhong , Jung-Suk Goo , Allison K. Holbrook , Joong S. Jeon , George J. Kluth
发明人： Qi Xiang , Huicai Zhong , Jung-Suk Goo , Allison K. Holbrook , Joong S. Jeon , George J. Kluth
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.
摘要翻译：根据一个示例性实施例，一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。该方法还包括在电介质层上沉积第一金属层。该方法还包括在第一金属层上沉积第二金属层。该方法还包括在衬底的NMOS区域中注入氮气，并将第一金属层的第一部分转变为金属氧化物层，并将第一金属层的第二部分转换为金属氮化物层。该方法还包括形成NMOS栅极和PMOS栅极，其中NMOS栅极包括一段金属氮化物层，PMOS栅极包括金属氧化物层的一段。

9. 发明授权

US06689687B1 Two-step process for nickel deposition 失效
标题翻译：镍沉积两步法
公开(公告)号：US06689687B1
公开(公告)日：2004-02-10
申请号：US10061348
申请日：2002-02-04
申请人： Jacques J. J. Bertrand , George J. Kluth
发明人： Jacques J. J. Bertrand , George J. Kluth
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/2855
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with xenon gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.
摘要翻译：亚微米尺寸的超浅结MOS和/或CMOS晶体管器件通过自对准硅化物工艺形成，其中覆盖镍层形成为与邻近侧壁间隔物的衬底表面的暴露部分接触，栅极的顶表面电极和侧壁间隔物。实施例包括通过以下顺序的步骤形成镍覆盖层：（i）通过溅射用氙气形成镍层; 和（ii）用氩气溅射形成镍层。用于形成镍覆盖层的两步工艺有利于防止在绝缘侧壁间隔物的外表面上形成硅化镍。

10. 发明授权

US06841449B1 Two-step process for nickel deposition 失效
标题翻译：镍沉积两步法
公开(公告)号：US06841449B1
公开(公告)日：2005-01-11
申请号：US10061345
申请日：2002-02-04
申请人： Jacques J. Bertrand , George J. Kluth
发明人： Jacques J. Bertrand , George J. Kluth
IPC分类号： H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： H01L29/665 , H01L21/28518
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices are formed by a salicide process wherein a blanket nickel layer is formed in contact with the exposed portions of the substrate surface adjacent the sidewall spacers, the top surface of the gate electrode, and the sidewall spacers. Embodiments include forming the blanket layer of nickel is formed by the sequential steps of: (i) forming a layer of nickel by sputtering with oxygen gas; and, (ii) forming a layer of nickel by sputtering with argon gas. The two step process for forming the blanket layer of nickel advantageously prevents the formation of nickel silicide on the outer surfaces of the insulative sidewall spacers.
摘要翻译：亚微米尺寸的超浅结MOS和/或CMOS晶体管器件通过自对准硅化物工艺形成，其中覆盖镍层形成为与邻近侧壁间隔物的衬底表面的暴露部分接触，栅极的顶表面电极和侧壁间隔物。实施例包括通过以下顺序的步骤形成镍覆盖层：（i）通过用氧气溅射形成镍层; 和（ii）用氩气溅射形成镍层。用于形成镍覆盖层的两步工艺有利于防止在绝缘侧壁间隔物的外表面上形成硅化镍。

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