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1. 发明授权

US06737703B1 Memory array with buried bit lines 失效
标题翻译：内存阵列带埋线
公开(公告)号：US06737703B1
公开(公告)日：2004-05-18
申请号：US10095512
申请日：2002-03-12
申请人： Richard Fastow , Sameer Haddad , Yu Sun
发明人： Richard Fastow , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a memory device, a substrate has a plurality of source/drain regions in the substrate. Between the source/drain regions are trenches filled with oxide. Individual bit lines in the form of conductive regions are provided in the substrate, each bit line being under and running along the oxide in a trench. Each bit line connects to source/drain regions by means of connecting conductive regions extending from that bit line to source/drain regions.
摘要翻译：在存储器件中，衬底在衬底中具有多个源极/漏极区域。在源极/漏极区之间是填充有氧化物的沟槽。导电区域形式的单个位线设置在衬底中，每个位线沿着沟槽中的氧化物在下面并且沿着其延伸。每个位线通过将从该位线延伸的导电区域连接到源极/漏极区域而连接到源极/漏极区域。

2. 发明授权

US06768683B1 Low column leakage flash memory array 失效
标题翻译：低列泄漏闪存阵列
公开(公告)号：US06768683B1
公开(公告)日：2004-07-27
申请号：US10095739
申请日：2002-03-12
申请人： Richard Fastow , Sameer Haddad
发明人： Richard Fastow , Sameer Haddad
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C5/063 , G11C16/0483
摘要： The present memory includes a plurality of transistors laid out in a number of rows and columns. First and second series-connected transistors are included in a first column, and are connected between first and second bit lines and are respectively associated with first and second word lines. A region between the series-connected first and second transistors is connected to a first bit line. Third and fourth series-connected transistors are included in a second column, and are connected between the second bit line and a third bit line and are respectively associated with third and fourth word lines. A region between the series-connected third and fourth transistors is connected to a second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors.
摘要翻译：本存储器包括布置在多个行和列中的多个晶体管。第一和第二串联晶体管被包括在第一列中，并且连接在第一和第二位线之间，并且分别与第一和第二字线相关联。串联的第一和第二晶体管之间的区域连接到第一位线。第三和第四串联晶体管被包括在第二列中，并且连接在第二位线和第三位线之间，并且分别与第三和第四字线相关联。串联的第三和第四晶体管之间的区域连接到第二位线。第一，第二，第三和第四晶体管是第一，第二，第三和第四行晶体管的相应部分。

3. 发明授权

US06700201B1 Reduction of sector connecting line capacitance using staggered metal lines 有权
标题翻译：使用交错金属线路减少扇区连接线路电容
公开(公告)号：US06700201B1
公开(公告)日：2004-03-02
申请号：US10013902
申请日：2001-12-11
申请人： Richard Fastow , Yue-Song He , Sameer Haddad
发明人： Richard Fastow , Yue-Song He , Sameer Haddad
IPC分类号： H01L2348
CPC分类号： H01L27/105 , Y10S257/906
摘要： In a memory array, a plurality of sectors are included. Each sector includes a plurality of parallel bit lines which lie in a plane. Sector connecting lines connect the sectors. These sector connecting lines are parallel to each other and to the bit lines. The sector connecting lines include a first set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the bit lines, and a second set of sector connecting lines which lie in a plane parallel to and adjacent and spaced from the plane of the first set of sector connecting lines. When viewed across the sector, consecutive sector connecting lines lie in the two different planes thereof in alternating manner, i.e., the sector connecting lines are in a staggered relation.
摘要翻译：在存储器阵列中，包括多个扇区。每个扇区包括位于平面中的多个并行位线。扇区连接线连接扇区。这些扇形连接线彼此平行并且与位线平行。扇形连接线包括第一组扇形连接线，它们位于与位线的平面平行且相邻并与其间隔开的平面中;以及第二组扇形连接线，其位于平行于并相邻并间隔开的平面中从第一套扇形连接线的平面。当跨扇区观看时，连续的扇区连接线以交替方式位于其两个不同的平面中，即扇区连接线处于交错关系。

4. 发明授权

US06646914B1 Flash memory array architecture having staggered metal lines 有权
标题翻译：具有交错金属线的闪存阵列架构
公开(公告)号：US06646914B1
公开(公告)日：2003-11-11
申请号：US10096313
申请日：2002-03-12
申请人： Sameer Haddad , Richard Fastow
发明人： Sameer Haddad , Richard Fastow
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C16/0416
摘要： A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing substantially strait elongated source/drain regions in side-by-side, parallel relation. Each bit line has a zigzag configuration and connects to a pair of adjacent source/drain regions in alternating manner along the bit line length.
摘要翻译：存储器阵列包括多组晶体管，每组晶体管包括串联的一对晶体管。每对这样的晶体管连接在一对相邻的位线之间。每组中的每对晶体管与相邻的一对字线中的不同的一个相关联。该阵列通过以并排的平行关系提供基本上两条细长的源极/漏极区域来配置。每个位线具有之字形配置并且沿着位线长度交替地连接到一对相邻的源极/漏极区域。

5. 发明授权

US06754109B1 Method of programming memory cells 有权
标题翻译：编程存储单元的方法
公开(公告)号：US06754109B1
公开(公告)日：2004-06-22
申请号：US10282847
申请日：2002-10-29
申请人： Richard Fastow , Sameer Haddad , Zhigang Wang , Sheung-Hee Park
发明人： Richard Fastow , Sameer Haddad , Zhigang Wang , Sheung-Hee Park
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： In the present method of programming a selected flash EEPROM memory cell of a pair thereof in series, a positive voltage is applied to the drain of the selected cell to be programmed, a voltage lower than the voltage applied to the drain is applied to the source of the selected cell, a negative voltage is applied to the substrate, and a positive voltage is applied to the control gate sufficient to induce hot electron injection from the drain to the floating gate of the selected cell.
摘要翻译：在本文对串联选择的一对闪存EEPROM存储单元进行编程的方法中，将正电压施加到要被编程的选定单元的漏极，低于施加到漏极的电压的电压施加到源极，向基板施加负电压，并且将正电压施加到控制栅极，足以引起从漏极到所选电池的浮置栅极的热电子注入。

6. 发明授权

US06953752B1 Reduced silicon gouging and common source line resistance in semiconductor devices 失效
标题翻译：在半导体器件中减少硅沟槽和普通源极线电阻
公开(公告)号：US06953752B1
公开(公告)日：2005-10-11
申请号：US10358756
申请日：2003-02-05
申请人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
发明人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
IPC分类号： H01L21/311 , H01L21/8247
CPC分类号： H01L27/11521
摘要： In the present method of undertaking a self aligned source etch of a semiconductor structure, a substrate has oxide thereon. First and second adjacent stacked gate structures are provided on the substrate. Oxide spacers are provided on the respective first and second adjacent sides of the first and second gate stacked structures, and polysilicon spacers are provided on the respective oxide spacers. A self aligned source etch is undertaken using the gate structures, oxide spacers, and polysilicon spacers as a mask. The polysilicon spacers are then removed, and metal, for example cobalt, is provided on the substrate, using the oxide spacers as a mask. A silicidation step is undertaken to form metal silicide common source line on the substrate.
摘要翻译：在进行半导体结构的自对准源蚀刻的本方法中，衬底在其上具有氧化物。第一和第二相邻的堆叠栅极结构设置在基板上。在第一和第二栅极堆叠结构的相应的第一和第二相邻侧上设置氧化物间隔物，并且在各个氧化物间隔物上设置多晶硅间隔物。使用栅极结构，氧化物间隔物和多晶硅间隔物作为掩模进行自对准源蚀刻。然后去除多晶硅间隔物，并且使用氧化物间隔物作为掩模在衬底上提供金属（例如钴）。进行硅化步骤以在衬底上形成金属硅化物共同源极线。

7. 发明申请

US20050077567A1 Memory cell array with staggered local inter-connect structure 失效
标题翻译：具有交错局部互连结构的存储单元阵列
公开(公告)号：US20050077567A1
公开(公告)日：2005-04-14
申请号：US10685044
申请日：2003-10-14
申请人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.
摘要翻译：存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。存储单元布置成多行和多列。每列存储单元包括多个交替沟道区和源极/漏极区。导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。另一个源/漏区位于与该列相邻的第二列中。导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

8. 发明授权

US06510085B1 Method of channel hot electron programming for short channel NOR flash arrays 有权
标题翻译：用于短通道NOR闪存阵列的通道热电子编程方法
公开(公告)号：US06510085B1
公开(公告)日：2003-01-21
申请号：US09861031
申请日：2001-05-18
申请人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
发明人： Richard Fastow , Sheunghee Park , Zhigang Wang , Sameer Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, between 4 and 5.5 volts is applied to the drains, between 0.5 and 2 volts is applied to the sources and between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells.
摘要翻译：编程和软编程短节目NOR闪存单元的方法，可在编程和软编程期间减少编程电流和列泄漏，同时保持快速的编程速度。在编程期间，7至10伏之间的电压施加到控制栅极，电压在4和6伏之间; 施加到漏极，将0.5至2.0伏之间的电压施加到源极，并且在所述要编程的所选择的单元的衬底之间施加负2和负0.5伏之间的电压。在软编程期间，向控制栅极施加0.5至4.5伏之间的电压，在漏极之间施加4至5.5伏之间的电压，施加0.5至2伏之间的电压，并施加负2.0至负0.5伏之间到存储单元的基板。

9. 发明授权

US06583009B1 Innovative narrow gate formation for floating gate flash technology 有权
标题翻译：用于浮栅闪存技术的创新窄门形成
公开(公告)号：US06583009B1
公开(公告)日：2003-06-24
申请号：US10178106
申请日：2002-06-24
申请人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
发明人： Angela T. Hui , Kelwin Ko , Hiroyuki Kinoshita , Sameer Haddad , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/952
摘要： The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.
摘要翻译：本发明涉及一种形成层叠栅极闪存单元的方法，包括在半导体衬底上连续形成隧道氧化物层，第一导电层，多晶硅间介质层和第二导电层。该方法还包括在第二导电层上形成牺牲层，以及图案化牺牲层以形成具有与其相关联的至少一个侧向侧壁边缘的牺牲层特征。然后在牺牲层的横向侧壁边缘上形成侧壁间隔物，其中间隔件具有与其相关联的宽度，并且去除图案化的牺牲层特征。最后，使用间隔物作为硬掩模来图案化第二导电层，多晶硅间电介质和第一导电层，并且限定堆叠栅极，其中堆叠栅极的宽度是间隔物宽度的函数。

10. 发明授权

US6001713A Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中的浮栅和互聚电介质层中形成富氮区的方法
公开(公告)号：US6001713A
公开(公告)日：1999-12-14
申请号：US154074
申请日：1998-09-16
申请人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
发明人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
IPC分类号： H01L21/28 , H01L21/265
CPC分类号： H01L21/28273
摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.
摘要翻译：提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。这在浮动栅极内形成初始氮浓度分布。然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

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