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1. 发明授权

US07240203B2 Method and apparatus for establishing secure sessions 有权
标题翻译：用于建立安全会话的方法和装置
公开(公告)号：US07240203B2
公开(公告)日：2007-07-03
申请号：US10025509
申请日：2001-12-19
申请人： Richard E. Kessler , David A. Carlson , Muhammad Raghib Hussain , Robert A. Sanzone , Khaja E. Ahmed , Michael D. Varga
发明人： Richard E. Kessler , David A. Carlson , Muhammad Raghib Hussain , Robert A. Sanzone , Khaja E. Ahmed , Michael D. Varga
IPC分类号： H04L9/00
CPC分类号： H04L63/164 , G06F21/606
摘要： A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.
摘要翻译：描述用于处理安全操作的方法和装置。在一个实施例中，处理器包括多个执行单元，用于处理多个安全操作请求。执行单元的数量是基于存储在请求数中的指针，将与多个与远程存储器内的请求数相关联的输出数据结构的请求数的结果输出。执行单元的数量可以按照与请求队列中的请求顺序不同的顺序输出结果。处理器还包括耦合到执行单元数量的请求单元。请求单元从远程存储器中的请求队列中检索一部分请求数，并且从远程存储器中获取部分请求的相关联的输入数据结构。此外，请求单元是基于执行单元的数量的处理的可用性将检索到的请求分发到执行单元的数量。

2. 发明授权

US06789147B1 Interface for a security coprocessor 有权
标题翻译：用于安全协处理器的接口
公开(公告)号：US06789147B1
公开(公告)日：2004-09-07
申请号：US10025512
申请日：2001-12-19
申请人： Richard E. Kessler , David A. Carlson , Muhammad Raghib Hussain , Robert A. Sanzone , Khaja E. Ahmed , Michael D. Varga
发明人： Richard E. Kessler , David A. Carlson , Muhammad Raghib Hussain , Robert A. Sanzone , Khaja E. Ahmed , Michael D. Varga
IPC分类号： G06F900
CPC分类号： H04L63/166 , G06F21/602
摘要： A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.
摘要翻译：描述用于处理安全操作的方法和装置。在一个实施例中，处理器包括多个执行单元，用于处理多个安全操作请求。执行单元的数量是基于存储在请求数中的指针，将与多个与远程存储器内的请求数相关联的输出数据结构的请求数的结果输出。执行单元的数量可以按照与请求队列中的请求顺序不同的顺序输出结果。处理器还包括耦合到执行单元数量的请求单元。请求单元从远程存储器中的请求队列中检索一部分请求数，并且从远程存储器中获取部分请求的相关联的输入数据结构。此外，请求单元是基于执行单元的数量的处理的可用性将检索到的请求分发到执行单元的数量。

3. 发明授权

US08356194B2 Method and apparatus for estimating overshoot power after estimating power of executing events 有权
标题翻译：估计执行事件功率后估计过冲功率的方法和装置
公开(公告)号：US08356194B2
公开(公告)日：2013-01-15
申请号：US12695648
申请日：2010-01-28
申请人： David A. Carlson , Richard E. Kessler , Amer Haider
发明人： David A. Carlson , Richard E. Kessler , Amer Haider
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3206 , G06F1/206 , G06F1/32 , G06F1/3203 , G06F1/329 , G06F11/3058 , Y02D10/24 , Y10S323/907
摘要： Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.
摘要翻译：本发明的实施例涉及限制在处理器中发生的最大功率耗散。因此，当正在执行需要过多功率的应用时，可以防止应用的执行以减少耗散或消耗的功率。示例性实施例可以阻止处理器发出或执行指令，允许软件或硬件通过施加应用的性能的降低而降低应用的功率。

4. 发明申请

US20110185203A1 METHOD AND APPARATUS FOR POWER CONTROL 有权
标题翻译：用于功率控制的方法和装置
公开(公告)号：US20110185203A1
公开(公告)日：2011-07-28
申请号：US12695648
申请日：2010-01-28
申请人： David A. Carlson , Richard E. Kessler , Amer Haider
发明人： David A. Carlson , Richard E. Kessler , Amer Haider
IPC分类号： G06F1/00
CPC分类号： G06F1/3206 , G06F1/206 , G06F1/32 , G06F1/3203 , G06F1/329 , G06F11/3058 , Y02D10/24 , Y10S323/907
摘要： Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.
摘要翻译：本发明的实施例涉及限制在处理器中发生的最大功率耗散。因此，当正在执行需要过多功率的应用时，可以防止应用的执行以减少耗散或消耗的功率。示例性实施例可以阻止处理器发出或执行指令，允许软件或硬件通过施加应用的性能的降低而降低应用的功率。

5. 发明授权

US07941585B2 Local scratchpad and data caching system 有权
标题翻译：本地暂存器和数据缓存系统
公开(公告)号：US07941585B2
公开(公告)日：2011-05-10
申请号：US11015343
申请日：2004-12-17
申请人： David H. Asher , David A. Carlson , Richard E. Kessler
发明人： David H. Asher , David A. Carlson , Richard E. Kessler
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/084 , G06F9/30014 , G06F9/30138 , G06F9/383 , G06F11/3632 , G06F12/0804 , G06F12/0813 , G06F12/0815 , G06F12/0835 , G06F12/0875 , G06F12/0891 , G06F13/24 , G06F2212/6012 , G06F2212/6022
摘要： A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.
摘要翻译： RISC型处理器包括主寄存器文件和数据高速缓存。可以将数据高速缓存分割成包括本地存储器，当处理器正在执行使用主寄存器文件的指令时，可以在缓存块的基础上动态地改变其大小。本地存储器可以作为额外的寄存器文件模拟到处理器，并且可以驻留在虚拟地址处。本地存储器可以被进一步分区以从不可缓存地址预取数据以被存储/加载到主寄存器文件中。

6. 发明授权

US08392590B2 Deterministic finite automata (DFA) processing 有权
标题翻译：确定性有限自动机（DFA）处理
公开(公告)号：US08392590B2
公开(公告)日：2013-03-05
申请号：US11221408
申请日：2005-09-07
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
IPC分类号： G06F15/16 , G06F17/28
CPC分类号： H04L49/90 , G06F15/7846 , H04L29/06 , H04L63/02 , H04L63/04 , H04L63/145 , H04L63/164 , H04L69/12
摘要： A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.
摘要翻译：用于实时传入传入分组数据的运行确定性有限自动机（DFA）图的处理器。所述处理器包括至少一个处理器核心和与所述至少一个处理器核心异步操作的DFA模块，用于使用存储在高速缓存相干存储器中的分组数据遍历存储在非高速缓冲存储器中的至少一个DFA图形。

7. 发明授权

US08301788B2 Deterministic finite automata (DFA) instruction 有权
标题翻译：确定性有限自动机（DFA）指令
公开(公告)号：US08301788B2
公开(公告)日：2012-10-30
申请号：US11220899
申请日：2005-09-07
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
IPC分类号： G06F15/16 , G06F15/173 , H04L12/28 , H04J3/06
CPC分类号： G06F9/30003 , H04L1/0045
摘要： A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.
摘要翻译：描述了一种用于遍历确定性有限自动机（DFA）图的计算机可读指令，以便在即将进行的分组数据中实时地执行模式搜索。该指令包括一个或多个预定义字段。其中一个字段包括用于标识几个先前存储的DFA图形之一的DFA图形标识符。另一个领域包括用于使用所识别的DFA图形来识别要处理的输入数据的输入参考。另一个领域包括用于存储响应于经处理的输入数据生成的结果的输出参考。这些指令被转发到适用于使用识别的DFA图处理输入数据的DFA引擎，并根据输出参考的指示提供结果。

8. 发明授权

US07594081B2 Direct access to low-latency memory 有权
标题翻译：直接访问低延迟内存
公开(公告)号：US07594081B2
公开(公告)日：2009-09-22
申请号：US11024002
申请日：2004-12-28
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3824 , G06F9/3885 , G06F12/0888
摘要： A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.
摘要翻译：提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。非普通的加载/存储指令可以是协处理器指令。存储器可以是低延迟型存储器。处理器可以包括多个处理器核。

9. 发明授权

US07558925B2 Selective replication of data structures 有权
标题翻译：数据结构的选择性复制
公开(公告)号：US07558925B2
公开(公告)日：2009-07-07
申请号：US11335189
申请日：2006-01-18
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F12/0653 , G06F2212/174
摘要： Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).
摘要翻译：提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

10. 发明授权

US08456331B2 System and method of compression and decompression 有权
公开(公告)号：US08456331B2
公开(公告)日：2013-06-04
申请号：US13087817
申请日：2011-04-15
申请人： David A. Carlson
发明人： David A. Carlson
IPC分类号： H03M7/34
CPC分类号： H03M7/3084 , H03M7/3086 , H03M7/40 , H03M7/425 , H03M7/6005 , H03M7/607
摘要： The disclosure relates to a system and a method for hardware encoding and decoding according to the Limpel Ziv STAC (LZS) and Deflate protocols based upon a configuration bit.

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