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1. 发明授权

US07113048B2 Ultra high frequency ring oscillator with voltage controlled frequency capabilities 失效
标题翻译：具有电压控制频率功能的超高频环形振荡器
公开(公告)号：US07113048B2
公开(公告)日：2006-09-26
申请号：US10988463
申请日：2004-11-12
申请人： Richard B. Brown , Gary D. Carpenter , Fadi H. Gebara
发明人： Richard B. Brown , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03B5/24 , H03K3/03 , H03L7/099
CPC分类号： H03K3/0315 , H03K3/356139 , H03K5/133 , H03L7/0995
摘要： A pseudo Set/Reset latch circuit is configured with modified NOR or NAND gates wherein one of the series pull-up devices or pull-down devices is removed. A minimum of three pseudo Set/Reset latches may be coupled as a ring oscillator generating an output and a non-skewed complementary output. Additionally, feed-forward inverting stages may be coupled in parallel with inverting paths in the ring oscillator primary path to further increase the frequency range of the ring oscillator. The pseudo Set/Reset latch circuits and the feed-forward inverting stages may be configured with voltage controlled devices that alter the delay of the stages as a means for varying the frequency of the ring oscillator either by varying the current drive of the circuitry driving the output of the latch stages or by varying the conductance of devices coupling between the latch stages. Feedforward inverting stages may comprise pseudo latches or inverter gates.
摘要翻译：伪置位/复位锁存电路配置有修改的NOR或NAND门，其中串联上拉器件或下拉器件中的一个被去除。可以将至少三个伪设置/复位锁存器耦合作为产生输出和非偏斜互补输出的环形振荡器。此外，前馈反相级可以与环形振荡器主路径中的反相路径并联耦合，以进一步增加环形振荡器的频率范围。伪设置/复位锁存电路和前馈反相级可以配置有电压控制的装置，其通过改变驱动电路的电路的电流驱动来改变级的延迟，作为改变环形振荡器的频率的手段锁存级的输出或通过改变耦合在锁存级之间的器件的电导。前馈反相级可以包括伪锁存器或反相器门。

2. 发明授权

US07667513B2 Digital duty cycle corrector 失效
标题翻译：数字占空比校正器
公开(公告)号：US07667513B2
公开(公告)日：2010-02-23
申请号：US10988454
申请日：2004-11-12
申请人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
发明人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译：公开了一种校正数字信号占空比的电路和方法。测量输入数字信号的占空比并将其与期望的占空比进行比较。输入数字信号的前沿被传递到输出。该电路和方法调节输出端的下降沿以达到所需的占空比。响应于延迟版本的输入数字信号的上升沿发生下降沿。

3. 发明申请

US20100102854A1 CIRCULAR EDGE DETECTOR 失效
标题翻译：圆形边缘检测器
公开(公告)号：US20100102854A1
公开(公告)日：2010-04-29
申请号：US12621763
申请日：2009-11-19
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

4. 发明授权

US07668037B2 Storage array including a local clock buffer with programmable timing 有权
标题翻译：存储阵列包括具有可编程时序的本地时钟缓冲器
公开(公告)号：US07668037B2
公开(公告)日：2010-02-23
申请号：US11935566
申请日：2007-11-06
申请人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/14 , G11C29/50 , G11C29/50012
摘要： A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaluate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.
摘要翻译：包括具有可编程时序的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。本地时钟缓冲器可以独立调节控制字线和本地位线预充电脉冲的本地时钟的脉冲宽度以及控制全局位线预充电，评估和读取数据锁存的延迟时钟的脉冲宽度。本地时钟和延迟时钟之间的延迟也可以调整。通过改变本地和延迟的时钟信号的脉冲宽度以及时钟间延迟，可以通过读取和写入具有变化的脉冲宽度和时钟延迟的单元来评估阵列中每个单元的定时裕度。所得到的评估可用于评估管芯内的时间裕度变化，以及在管芯到管芯之间以及在变化的环境（例如电压和温度变化）下的变化。

5. 发明申请

US20090116312A1 Storage Array Including a Local Clock Buffer with Programmable Timing 有权
标题翻译：包括具有可编程时序的本地时钟缓冲器的存储阵列
公开(公告)号：US20090116312A1
公开(公告)日：2009-05-07
申请号：US11935566
申请日：2007-11-06
申请人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Fadi H. Gebara , Jerry C. Kao , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C29/02 , G11C29/023 , G11C29/14 , G11C29/50 , G11C29/50012
摘要： A storage array including a local clock buffer with programmable timing provides a mechanism for evaluating circuit timing internal to the storage array. The local clock buffer can independently adjust the pulse width of a local clock that controls the wordline and local bitline precharge pulses and the pulse width of a delayed clock that controls the global bitline precharge, evaulate and read data latching. The delay between the local clock and the delayed clock can also be adjusted. By varying the pulse widths of the local and delayed clock signal, along with the inter-clock delay, the timing margins of each cell in the array can be evaluated by reading and writing the cell with varying pulse width and clock delay. The resulting evaluation can be used to evaluate timing margin variation within a die, as well variation from die-to-die and under varying environments, e.g., voltage and temperature variation.
摘要翻译：包括具有可编程时序的本地时钟缓冲器的存储阵列提供了用于评估存储阵列内部的电路定时的机制。本地时钟缓冲器可以独立调节控制字线和本地位线预充电脉冲的本地时钟的脉冲宽度以及控制全局位线预充电，延迟和读取数据锁存的延迟时钟的脉冲宽度。本地时钟和延迟时钟之间的延迟也可以调整。通过改变本地和延迟的时钟信号的脉冲宽度以及时钟间延迟，可以通过读取和写入具有变化的脉冲宽度和时钟延迟的单元来评估阵列中每个单元的定时裕度。所得到的评估可用于评估管芯内的时间裕度变化，以及在管芯到管芯之间以及在变化的环境（例如电压和温度变化）下的变化。

6. 发明申请

US20080122490A1 Circular Edge Detector 失效
标题翻译：圆形边缘检测器
公开(公告)号：US20080122490A1
公开(公告)日：2008-05-29
申请号：US11563888
申请日：2006-11-28
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

7. 发明授权

US07759980B2 Circular edge detector for measuring timing of data signals 失效
标题翻译：用于测量数据信号定时的圆形边缘检测器
公开(公告)号：US07759980B2
公开(公告)日：2010-07-20
申请号：US11563888
申请日：2006-11-28
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

8. 发明授权

US07288975B2 Method and apparatus for fail-safe and restartable system clock generation 失效
公开(公告)号：US07288975B2
公开(公告)日：2007-10-30
申请号：US11260563
申请日：2005-10-27
申请人： Hung C. Ngo , Gary D. Carpenter , Fadi H. Gebara , Jente B. Kuang
发明人： Hung C. Ngo , Gary D. Carpenter , Fadi H. Gebara , Jente B. Kuang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , G06F1/04
摘要： A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

9. 发明授权

US08212537B2 Integratable efficient switching down converter 有权
标题翻译：可集成的高效切换转换器
公开(公告)号：US08212537B2
公开(公告)日：2012-07-03
申请号：US12508235
申请日：2009-07-23
申请人： Gary D. Carpenter , Wonyoung Kim , Brian L. Ji
发明人： Gary D. Carpenter , Wonyoung Kim , Brian L. Ji
IPC分类号： G05F1/10 , G05F1/40
CPC分类号： H02M3/158
摘要： A converter circuit and methods for operating the same. The converter circuit includes a supply voltage, a capacitor, an inductor, and four stacked switching elements. Each switching element is adjustable from a low resistance state to a high resistance state by a control signal. The inductor outputs current to a circuit load. The circuit may be operated in a first mode such that the output is adjustable between the supply voltage and half the supply voltage. Alternatively, in a second mode of operation, the output is adjustable from half the supply voltage to a ground voltage.
摘要翻译： A转换器电路及其操作方法。转换器电路包括电源电压，电容器，电感器和四个堆叠的开关元件。每个开关元件可通过控制信号从低电阻状态调节到高电阻状态。电感将电流输出到电路负载。电路可以在第一模式下操作，使得输出在电源电压和电源电压的一半之间是可调节的。或者，在第二操作模式中，输出可从电源电压的一半调整到接地电压。

10. 发明申请

US20120124669A1 Hindering Side-Channel Attacks in Integrated Circuits 审中-公开
标题翻译：在集成电路中受阻的侧向通道攻击
公开(公告)号：US20120124669A1
公开(公告)日：2012-05-17
申请号：US12945155
申请日：2010-11-12
申请人： Gary D. Carpenter , Eren Kursun , Phillip J. Restle , Michael R. Scheuermann
发明人： Gary D. Carpenter , Eren Kursun , Phillip J. Restle , Michael R. Scheuermann
IPC分类号： G06F21/00
CPC分类号： G06F21/86 , G06F21/71 , G06F21/755
摘要： A mechanism is provided for protecting a layer of functional units from side-channel attacks. A determination is made as to whether one or more subsets of functional units in a set of functional units in the layer of functional units is performing operations of a critical nature. Responsive to a determination that there is one or more subsets of functional units that are performing the operations of the critical nature, at least one concealing pattern is generated in a concealing layer in order to conceal the operations of the critical nature being performed by each of the subset of functional units. The concealing layer is electrically and physically coupled to the layer of functional units.
摘要翻译：提供了用于保护功能单元层免受侧信道攻击的机制。确定功能单元层中的一组功能单元中的一个或多个功能单元的子集是否执行关键性质的操作。响应于确定存在正在执行关键性质的操作的功能单元的一个或多个子集，在隐藏层中生成至少一个隐藏模式，以便隐藏正在执行的关键性质的操作功能单元的子集。隐藏层电性和物理耦合到功能单元层。

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