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1. 发明授权

US07667513B2 Digital duty cycle corrector 失效
标题翻译：数字占空比校正器
公开(公告)号：US07667513B2
公开(公告)日：2010-02-23
申请号：US10988454
申请日：2004-11-12
申请人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
发明人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译：公开了一种校正数字信号占空比的电路和方法。测量输入数字信号的占空比并将其与期望的占空比进行比较。输入数字信号的前沿被传递到输出。该电路和方法调节输出端的下降沿以达到所需的占空比。响应于延迟版本的输入数字信号的上升沿发生下降沿。

2. 发明授权

US07216141B2 Computing carry-in bit to most significant bit carry save adder in current stage 失效
标题翻译：计算进位位到当前阶段的最高有效位进位保存加法器
公开(公告)号：US07216141B2
公开(公告)日：2007-05-08
申请号：US10702992
申请日：2003-11-06
申请人： Wendy A. Belluomini , Ramyanshu Datta , Jente Benedict Kuang , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
发明人： Wendy A. Belluomini , Ramyanshu Datta , Jente Benedict Kuang , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
IPC分类号： G06F7/50
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要翻译：一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位前一阶段通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟由高阶全加器。

3. 发明授权

US07284029B2 4-to-2 carry save adder using limited switching dynamic logic 失效
标题翻译：使用有限切换动态逻辑的4对2进位保存加法器
公开(公告)号：US07284029B2
公开(公告)日：2007-10-16
申请号：US10702989
申请日：2003-11-06
申请人： Wendy A. Belluomini , Ramyanshu Datta , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
发明人： Wendy A. Belluomini , Ramyanshu Datta , Chandler T. McDowell , Robert K. Montoye , Hung C. Ngo
IPC分类号： G06F7/50
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.
摘要翻译：一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

4. 发明申请

US20070296442A1 Method and Apparatus for Measuring Device Mismatches 有权
标题翻译：用于测量设备不匹配的方法和设备
公开(公告)号：US20070296442A1
公开(公告)日：2007-12-27
申请号：US11422913
申请日：2006-06-08
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

5. 发明授权

US06769774B2 Ambient light tolerant image projection method and system 失效
标题翻译：环境容忍图像投影方法和系统
公开(公告)号：US06769774B2
公开(公告)日：2004-08-03
申请号：US10294990
申请日：2002-11-14
申请人： Chandler T. McDowell
发明人： Chandler T. McDowell
IPC分类号： G03B2114
CPC分类号： G03B21/005
摘要： A method and systems for projecting an image onto a screen in high ambient light. The image is composed as pixels comprising selected intensities of preselected bands of visible light. The pixels are created by modulating three frequencies of light corresponding to hues in the red, green, and blue spectrum. The modulated light selectively generates pixels of a frame of the image. A diffusive projection screen has a triple bandpass light filter surface that selectively transmits preselected bands of light frequencies around the red, green, and blue spectrums of the modulated light source. The triple bandpass light filter is used with projection screens in front and rear projection systems. The hues of red, green, and blue may be generated from LEDs or from extracting the frequencies from a broadband source. The modulator system may comprise a time multiplexed single modulator design or a triple modulator design.
摘要翻译：一种用于在高环境光下将图像投影到屏幕上的方法和系统。该图像被构成为包括所选择的可见光条带的强度的像素。通过调制对应于红色，绿色和蓝色光谱中的色调的三个光线来创建像素。调制光选择性地产生图像的帧的像素。扩散投影屏幕具有三重带通滤光器表面，其选择性地传输调制光源的红色，绿色和蓝色光谱周围的预选频谱带。三重带通滤光片与前投影系统和后投影系统中的投影屏幕一起使用。红色，绿色和蓝色的色调可能由LED产生，也可能是从宽带来源提取频率。调制器系统可以包括时间复用单调制器设计或三调制器设计。

6. 发明授权

US07622942B2 Method and apparatus for measuring device mismatches 失效
标题翻译：用于测量设备不匹配的方法和设备
公开(公告)号：US07622942B2
公开(公告)日：2009-11-24
申请号：US12147024
申请日：2008-06-26
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

7. 发明授权

US07408372B2 Method and apparatus for measuring device mismatches 有权
标题翻译：用于测量设备不匹配的方法和设备
公开(公告)号：US07408372B2
公开(公告)日：2008-08-05
申请号：US11422913
申请日：2006-06-08
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

8. 发明申请

US20080258752A1 METHOD AND APPARATUS FOR MEASURING DEVICE MISMATCHES 失效
标题翻译：用于测量设备错配的方法和装置
公开(公告)号：US20080258752A1
公开(公告)日：2008-10-23
申请号：US12147024
申请日：2008-06-26
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

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