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1. 发明授权

US07667513B2 Digital duty cycle corrector 失效
标题翻译：数字占空比校正器
公开(公告)号：US07667513B2
公开(公告)日：2010-02-23
申请号：US10988454
申请日：2004-11-12
申请人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
发明人： Gary D. Carpenter , Alan J. Drake , Fadi H. Gebara , Chandler T. McDowell , Hung C. Ngo
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译：公开了一种校正数字信号占空比的电路和方法。测量输入数字信号的占空比并将其与期望的占空比进行比较。输入数字信号的前沿被传递到输出。该电路和方法调节输出端的下降沿以达到所需的占空比。响应于延迟版本的输入数字信号的上升沿发生下降沿。

2. 发明申请

US20080122490A1 Circular Edge Detector 失效
标题翻译：圆形边缘检测器
公开(公告)号：US20080122490A1
公开(公告)日：2008-05-29
申请号：US11563888
申请日：2006-11-28
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

3. 发明申请

US20100102854A1 CIRCULAR EDGE DETECTOR 失效
标题翻译：圆形边缘检测器
公开(公告)号：US20100102854A1
公开(公告)日：2010-04-29
申请号：US12621763
申请日：2009-11-19
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

4. 发明授权

US07759980B2 Circular edge detector for measuring timing of data signals 失效
标题翻译：用于测量数据信号定时的圆形边缘检测器
公开(公告)号：US07759980B2
公开(公告)日：2010-07-20
申请号：US11563888
申请日：2006-11-28
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

5. 发明授权

US07810000B2 Circuit timing monitor having a selectable-path ring oscillator 失效
标题翻译：具有可选路径环形振荡器的电路定时监视器
公开(公告)号：US07810000B2
公开(公告)日：2010-10-05
申请号：US11559436
申请日：2006-11-14
申请人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
发明人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
IPC分类号： G01R31/3181 , G01R31/30
CPC分类号： G01R31/31727 , G01R31/31725 , G01R31/31726
摘要： An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.
摘要翻译：具有可选路径环形振荡器电路的在线定时监视器在实际电路环境中提供延迟和性能测量。测试模式信号被施加到数字电路以取消选择施加到数字电路内的功能逻辑块的给定功能输入信号，并且当选择测试模式操作时，将其与从功能逻辑块的输出耦合的反馈替换。选择从选择输入到输出的信号路径，使得信号路径振荡，并且测量输出信号的特征频率或相位以确定延迟。将功能逻辑块的其他输入设置为预定的一组逻辑值。可以在数字输入之前的寄存器处进行选择，或者在功能逻辑块的逻辑的第一级中进行选择。

6. 发明申请

US20080115019A1 Circuit Timing Monitor Having A Selectable-Path Ring Oscillator 失效
标题翻译：具有可选择路径环形振荡器的电路定时监视器
公开(公告)号：US20080115019A1
公开(公告)日：2008-05-15
申请号：US11559436
申请日：2006-11-14
申请人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
发明人： Hung C. Ngo , Gary D. Carpenter , Alan J. Drake , Jente B. Kuang
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/31725 , G01R31/31726
摘要： An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.
摘要翻译：具有可选路径环形振荡器电路的在线定时监视器在实际电路环境中提供延迟和性能测量。测试模式信号被施加到数字电路以取消选择施加到数字电路内的功能逻辑块的给定功能输入信号，并且当选择测试模式操作时，将其与从功能逻辑块的输出耦合的反馈替换。选择从选择输入到输出的信号路径，使得信号路径振荡，并且测量输出信号的特征频率或相位以确定延迟。将功能逻辑块的其他输入设置为预定的一组逻辑值。可以在数字输入之前的寄存器处进行选择，或者在功能逻辑块的逻辑的第一级中进行选择。

7. 发明授权

US07881135B2 Method for QCRIT measurement in bulk CMOS using a switched capacitor circuit 有权
标题翻译：使用开关电容电路的批量CMOS QCRIT测量方法
公开(公告)号：US07881135B2
公开(公告)日：2011-02-01
申请号：US11679406
申请日：2007-02-27
申请人： Ethan H. Cannon , Alan J. Drake , Fadi H. Gebara , John P. Keane , AJ Kleinosowski
发明人： Ethan H. Cannon , Alan J. Drake , Fadi H. Gebara , John P. Keane , AJ Kleinosowski
IPC分类号： G11C29/00
CPC分类号： G01R31/318594 , G01R31/318597
摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.
摘要翻译：用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。电压测量电路测量电荷注入前后电荷注入电路中的电压。当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。

8. 发明申请

US20080288197A1 Calibration of Multi-Metric Sensitive Delay Measurement Circuits 有权
标题翻译：多尺度敏感延迟测量电路的校准
公开(公告)号：US20080288197A1
公开(公告)日：2008-11-20
申请号：US11750475
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/02
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译：用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化的延迟电路。

9. 发明申请

US20080288196A1 Correction of Delay-Based Metric Measurements Using Delay Circuits Having Differing Metric Sensitivities 失效
标题翻译：使用具有不同公制灵敏度的延迟电路校正基于延迟的公制测量
公开(公告)号：US20080288196A1
公开(公告)日：2008-11-20
申请号：US11750385
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00 , G01R29/02
CPC分类号： G01R31/3016
摘要： Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.
摘要翻译：使用具有不同的度量灵敏度的延迟电路对基于延迟的度量测量进行校正为使用延迟线的环境和其他电路量度测量提供了改进的精度。可以使用对测量的特定度量具有不同灵敏度的至少两个延迟线来同时或顺序地执行可以是单次测量或环形振荡器频率测量的延迟线测量。校正电路或算法使用测量的延迟或环形振荡器频率，并根据其他延迟或环形振荡器频率来校正从延迟或环形振荡器频率之一确定的度量测量中的至少一个。延迟可以是逆变器链，一个链对电源电压的敏感性高于另一个延迟链，另一个延迟链对温度具有较高的灵敏度。然后可以对电源电压变化校正温度结果，反之亦然。

10. 发明授权

US07548823B2 Correction of delay-based metric measurements using delay circuits having differing metric sensitivities 失效
标题翻译：使用具有不同度量灵敏度的延迟电路校正基于延迟的度量测量
公开(公告)号：US07548823B2
公开(公告)日：2009-06-16
申请号：US11750385
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00
CPC分类号： G01R31/3016
摘要： Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.
摘要翻译：使用具有不同的度量灵敏度的延迟电路对基于延迟的度量测量进行校正为使用延迟线的环境和其他电路量度测量提供了改进的精度。可以使用对测量的特定度量具有不同灵敏度的至少两个延迟线来同时或顺序地执行可以是单次测量或环形振荡器频率测量的延迟线测量。校正电路或算法使用测量的延迟或环形振荡器频率，并根据其他延迟或环形振荡器频率来校正从延迟或环形振荡器频率之一确定的度量测量中的至少一个。延迟可以是逆变器链，一个链对电源电压的敏感性高于另一个延迟链，另一个延迟链对温度具有较高的灵敏度。然后可以对电源电压变化校正温度结果，反之亦然。

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