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1. 发明授权

US06493779B1 Method and system for interrupt handling using device pipelined packet transfers 失效
标题翻译：使用设备流水线分组传输的中断处理方法和系统
公开(公告)号：US06493779B1
公开(公告)日：2002-12-10
申请号：US09224111
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

2. 发明授权

US06418497B1 Method and system for interrupt handling using system pipelined packet transfers 失效
标题翻译：使用系统流水线分组传输的中断处理方法和系统
公开(公告)号：US06418497B1
公开(公告)日：2002-07-09
申请号：US09224119
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F948
CPC分类号： G06F13/26
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

3. 发明授权

US06182178B2 Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses 失效
标题翻译：支持通过支持多个PCI总线的PCI主机桥的外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US06182178B2
公开(公告)日：2001-01-30
申请号：US09106953
申请日：1998-06-30
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1338
CPC分类号： G06F13/4045
摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.
摘要翻译：公开了一种通过在数据处理系统内具有多个PCI接口的单个PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。根据本发明的方法和系统，处理器和系统存储器连接到系统总线。第一和第二PCI本地总线通过PCI主机桥连接到系统总线。第一和第二PCI本地总线具有一组在线电子开关，将PCI本地总线划分成支持用于连接PCI设备的多个PCI外围组件插槽的PCI本地总线段。根据PCI主机桥中的总线控制逻辑，这些在线电子开关是打开和关闭的，允许多达十四个或更多个PCI外设组件插槽，用于连接多达十四个PCI设备，以通过单个PCI主机桥访问系统总线。提供内部PCI至PCI桥接器，以允许PCI设备与第一和第二PCI本地总线段之间的对等设备与另一PCI设备共享数据。

4. 发明授权

US06240474B1 Pipelined read transfers 失效
标题翻译：流水线读取传输
公开(公告)号：US06240474B1
公开(公告)日：2001-05-29
申请号：US08931705
申请日：1997-09-16
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/28 , G06F13/4027
摘要： A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request.
摘要翻译：提供了一种实现流水线读取传输或PRT的方法和实现系统。 PRT包括请求阶段和响应阶段。 PRT请求阶段涉及PRT请求主机传送到PRT请求目标，源地址，目的地地址和正在请求的数据的传输大小。在PRT响应阶段，PRT请求目标成为PRT响应主机，即PCI总线主机，并启动完成在发起PRT请求中请求的事务。

5. 发明授权

US06185642B2 Bus for high frequency operation with backward compatibility and hot-plug ability 失效
标题翻译：高性能PCI总线，用于高频操作，具有向后兼容性和热插拔能力
公开(公告)号：US06185642B2
公开(公告)日：2001-02-06
申请号：US09116058
申请日：1998-07-15
申请人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
摘要翻译：一种用于包括桥接器，外围总线和外围设备的计算机系统的外设互连，其中这些组件中的至少一个适于选择性地以高性能模式或低性能模式操作，高性能模式使用第一操作速度和第一协议，以及使用低于所述第一操作速度的第二操作速度的低性能模式，以及不同于第一协议的第二协议。所公开的实施例提供具有100MHz速度的高性能模式和不允许起搏的协议，以及使用66MHz或33MHz速度的低性能模式和允许起搏的标准PCI协议。高性能运行速度可以是低性能运行速度的两倍，通过在一个时钟沿将时钟频率和时钟数据加倍，或者在时钟信号的上升沿和下降沿同时处理数据，同时在较低的时钟时钟频率。高性能适配器可以提供拆分事务功能，具有支持拆分事务或别名拆分事务延迟事务的高性能网桥。也可以向后兼容性提供可选功能，如热插拔。

6. 发明授权

US06175888B1 Dual host bridge with peer to peer support 失效
标题翻译：双主机桥与对等支持
公开(公告)号：US06175888B1
公开(公告)日：2001-01-16
申请号：US08627810
申请日：1996-04-10
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/36 , G06F13/4027
摘要： A data processing system includes a processor, system memory and a number of peripheral devices, and one or more bridges which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus. The host bridge provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces in provided.
摘要翻译：数据处理系统包括处理器，系统存储器和多个外围设备以及可以在处理器，存储器和外围设备以及诸如网络中的其它主机或外围设备之间连接的一个或多个桥接器。诸如PCI主机桥的桥连接在主总线（例如系统总线）和辅助总线之间。主桥提供双主机桥功能，其创建两个辅助总线接口。这允许在一个双主机桥下增加负载能力，而在一个正常主桥下允许的较少数量的时隙。还包括附加的控制逻辑，用于提供仲裁控制和用于转向事务到适当的总线接口。另外，提供的两个辅助总线接口的对等支持。

7. 发明授权

US6134621A Variable slot configuration for multi-speed bus 失效
标题翻译：多速总线可变插槽配置
公开(公告)号：US6134621A
公开(公告)日：2000-10-17
申请号：US092153
申请日：1998-06-05
申请人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F13/14 , G06F13/40 , G06F13/00 , G06F1/08 , G06F13/38
CPC分类号： G06F13/4068
摘要： A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.
摘要翻译：提供了一种方法和装置，其中实现控制方案以使得PCI总线能够操作可以安装PCI设备的两个以上PCI插槽。检查PCI插槽以确定PCI设备是否安装在插槽中以及安装的PCI设备能够运行的速度。如果任何插槽中的任何一个插槽中都安装了一个33 MHz器件，则系统可以运行多于两个插槽，所有PCI设备将以33 MHz运行。当PCI插槽中没有安装33 MHz的卡或设备时，PCI设备仅安装在前两个插槽中，则系统只能以66 MHz的速度运行前两个插槽。在一个替代实施例中，默认配置例程将PCI总线速度设置为工作频率之一，并且如果在系统配置周期期间确定另一个速度更合适，则修改该默认值。

8. 发明授权

US6035355A PCI system and adapter requirements following reset 失效
标题翻译：复位后的PCI系统和适配器要求
公开(公告)号：US6035355A
公开(公告)日：2000-03-07
申请号：US67042
申请日：1998-04-27
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F13/10 , G06F9/445 , G06F13/14 , G06F13/00
CPC分类号： G06F9/4411
摘要： A method of registering a newly added peripheral device with a computer system by responding with a status message from the device to a bus of the computer system, in response to an access attempt, and within a predetermined time period from the deasserting of the reset signal applied to device, so as to avoid stalling and thereby avoid the need to reboot the system in order to initialize the new peripheral device with the operating system. The device may be allowed to initially send a retry response, provided the response occurs during an initial latency period which is less than the predetermined time period. The invention also enables the peripheral device to respond to non-configuration cycles immediately following configuration completion. Internal logic of the peripheral device can be initialized after responding with the status message. Non-configuration access to the peripheral device can be prevented until it is ready to respond, by setting a bit (in the configuration space of the peripheral device to indicate that the peripheral device is ready.
摘要翻译：一种通过响应于访问尝试而将来自设备的状态消息与计算机系统的总线进行响应的计算机系统注册新添加的外围设备的方法，并且在从复位信号的解除的预定时间段内应用于设备，以避免停顿，从而避免重新启动系统以便使用操作系统初始化新的外围设备。如果响应发生在小于预定时间段的初始等待时间期间，则可以允许该设备最初发送重试响应。本发明还使外围设备能够在配置完成之后立即响应非配置周期。外部设备的内部逻辑可以在响应状态消息后进行初始化。可以通过设置一个位（在外围设备的配置空间中指示外围设备准备好）来准备好响应外部设备的非配置访问。

9. 发明授权

US06718422B1 Enhanced bus arbiter utilizing variable priority and fairness 失效
标题翻译：增强总线仲裁器利用可变优先权和公平性
公开(公告)号：US06718422B1
公开(公告)日：2004-04-06
申请号：US09363947
申请日：1999-07-29
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1336
CPC分类号： G06F13/364 , G06F13/4031
摘要： A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.
摘要翻译：一种用于计算机系统的总线仲裁器，其具有用于连接到多个总线设备的总线，其中每个总线设备通过使用总线请求信号来请求总线的控制。总线仲裁器包含逻辑，其包含用于基于每个总线设备的预定优先级和每个总线设备在公平循环内的先前访问来控制和优先化总线请求信号的公平方案。每个设备的先前访问由数据寄存器中的位跟踪，并且由设备是否实际上通过总线接收或发送信息而不是简单地授予可能导致重试信号的访问来确定。

10. 发明授权

US06295568B1 Method and system for supporting multiple local buses operating at different frequencies 失效
标题翻译：支持多个本地总线工作在不同频率的方法和系统
公开(公告)号：US06295568B1
公开(公告)日：2001-09-25
申请号：US09055414
申请日：1998-04-06
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1338
CPC分类号： G06F13/4022
摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. One or more PCI local buses are connected to the system bus through a single PCI host bridge having bus and frequency control logic and bus clocks. The PCI local buses include sets of in-line electronic switches, dividing each PCI local bus into PCI local bus segments for supporting more PCI peripheral component slots then are called out by the PCI local bus standard. The sets of in-line electronic switches are open and closed in accordance with the bus and frequency control logic within the PCI host bridge thereby allowing the PCI peripheral component slots to operate at different bus frequencies, including bus frequencies higher than 66 MHz by using the bus clocks. The sets of in-line electronic switches further allowing different bus segments on the same PCI logical bus to dynamically be operated at different frequencies.
摘要翻译：公开了一种通过在数据处理系统内具有多个PCI接口的单个PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。根据本发明的方法和系统，处理器和系统存储器连接到系统总线。一个或多个PCI本地总线通过具有总线和频率控制逻辑和总线时钟的单个PCI主机桥连接到系统总线。 PCI本地总线包括一系列在线电子开关，将每个PCI本地总线划分为PCI本地总线段，以支持更多的PCI外设组件插槽，然后由PCI本地总线标准进行调用。这些串联式电子开关根据PCI主机桥内的总线和频率控制逻辑开启和关闭，从而允许PCI外设组件插槽在不同的总线频率下工作，包括高于66MHz的总线频率，通过使用总线时钟这些在线电子开关进一步允许在同一PCI逻辑总线上的不同总线段动态地以不同的频率工作。

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