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1. 发明授权

US5122778A Serial word comparator 失效
标题翻译：串行字比较器
公开(公告)号：US5122778A
公开(公告)日：1992-06-16
申请号：US679811
申请日：1991-03-28
申请人： Richard A. Erhart , Walter L. Davis , Barry W. Herold
发明人： Richard A. Erhart , Walter L. Davis , Barry W. Herold
IPC分类号： G06F7/02 , G06F11/00 , H04W88/02
CPC分类号： H04W88/026 , G06F11/0763 , G06F7/02 , G06F2207/025
摘要： An apparatus for determining if a received binary word corresponds to the true or complement version of a stored binary word includes means for serially multiplexing the bits of each binary word to the inputs of an exclusive OR gate. The exclusive-OR gate generates a logical high signal each time a mismatch occurs. These signals are applied directly to an error counter and, after inversion, to a match counter. The contents of the error counter and match counter are compared to a stored threshold number. A first signal is generated if the contents of the error counter exceeds the threshold. A second signal is generated if the contents of the match counter exceeds the threshold. Upon the occurrence of both signals, the serial comparison process is terminated.
摘要翻译：一种用于确定接收的二进制字是否对应于所存储的二进制字的真实或补充版本的装置包括用于将每个二进制字的比特串行复用到异或门的输入的装置。每当发生不匹配时，异或门产生逻辑高电平信号。这些信号直接应用于错误计数器，并在反转后应用于匹配计数器。将错误计数器和匹配计数器的内容与存储的阈值进行比较。如果错误计数器的内容超过阈值，则生成第一个信号。如果匹配计数器的内容超过阈值，则产生第二个信号。发生两个信号时，串行比较处理结束。

2. 发明授权

US5128632A Adaptive lock time controller for a frequency synthesizer and method therefor 失效
标题翻译：用于频率合成器的自适应锁定时间控制器及其方法
公开(公告)号：US5128632A
公开(公告)日：1992-07-07
申请号：US700966
申请日：1991-05-16
申请人： Richard A. Erhart , Omid Tahernia , Barry W. Herold
发明人： Richard A. Erhart , Omid Tahernia , Barry W. Herold
IPC分类号： H03L7/089 , H03L7/095 , H03L7/107 , H03L7/199
CPC分类号： H03L7/0898 , H03L7/095 , H03L7/107 , H03L7/199 , Y10S331/02
摘要： An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked. The control signal selector selects the first control signal during the predetermined time interval when the phase unlocked condition is detected, and the second control signal when the phase locked condition is detected.
摘要翻译：一种用于锁相环的自适应锁定时间控制器，具有用于产生第一和第二环路定时信号的分频器，相位检测器，压控振荡器和充电电路，用于产生至少第一控制信号，用于将输出频率收敛到一个或更多的预定频率信道和用于维持输出频率基本恒定的第二控制信号包括同步发生器，锁相检测器和控制信号选择器。同步发生器响应于相位检测器以使相位锁定检测器同步。锁相检测器通过产生表示第一和第二环路定时信号之间的相位差的计数来检测锁相和解锁状态。当产生的计数超过预定计数时，存在锁相条件，否则循环被解锁。控制信号选择器在检测到相位解锁状态的预定时间间隔期间选择第一控制信号，并且在检测到锁相条件时选择第二控制信号。

3. 发明授权

US5063533A Reconfigurable deinterleaver/interleaver for block oriented data 失效
标题翻译：面向面向数据的可重构解交织器/交织器
公开(公告)号：US5063533A
公开(公告)日：1991-11-05
申请号：US335394
申请日：1989-04-10
申请人： Richard A. Erhart , Barry W. Herold , Joan S. DeLuca
发明人： Richard A. Erhart , Barry W. Herold , Joan S. DeLuca
IPC分类号： G06F7/78 , G06F12/06 , H03M13/27
CPC分类号： G06F7/785 , G11C7/1012 , G11C8/10 , G11C8/16 , H03M13/2703 , H03M13/2789
摘要： A reconfigurable deinterleaver for deinterleaving up to N interleaved codewords, each up to M bits in length comprises a memory array, a memory for storing predetermined deinterleaver parameters, a controller, and column and row selector means. The memory array is configured with N bit rows by M bit columns, and is capable of selectably deinterleaving interleaved codewords. The predetermined deinterleaver parameters define the number and length of the interleaved codewords to be deinterleaved. The controller is responsive to the deinterleaver parameters for controlling the writing of interleaved codewords into the memory array and for reading deinterleaved codewords from the memory array. Column and row selector means provide for writing interleaved codewords into, and reading deinterleaved codewords from only a portion of the memory array when smaller data blocks are deinterleaved.
摘要翻译：用于去交织多达N个交错码字的可重配置解交织器，每个高达M位的长度包括存储器阵列，用于存储预定去交织器参数的存储器，控制器和列和行选择器装置。存储器阵列配置有N位行×M位列，并且能够可选择地对交织的码字进行解交织。预定的去交织器参数定义要解交织的交错码字的数量和长度。控制器响应于去交织器参数来控制交织的码字的写入到存储器阵列中，并用于从存储器阵列读取解交织的码字。列和行选择器意味着提供将交织的码字写入并且当较小的数据块被去交错时从仅存储器阵列的一部分读取解交织的码字。

4. 发明授权

US5604449A Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes 失效
标题翻译：采用低电压CMOS工艺的高压CMOS电路的双I / O逻辑
公开(公告)号：US5604449A
公开(公告)日：1997-02-18
申请号：US592920
申请日：1996-01-29
申请人： Richard A. Erhart , Thomas W. Ciccone
发明人： Richard A. Erhart , Thomas W. Ciccone
IPC分类号： H03K19/003
CPC分类号： H03K19/00315
摘要： CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by providing each input signal as dual input signals that track each other within two different voltage ranges. A shield voltage is provided approximately midway between the uppermost and lowermost power supply voltages. The first input signal ranges between the lowermost power supply voltage and the shield voltage, and the second input signal ranges between the shield voltage and the uppermost power supply voltage. The first and second input signals drive the gates of n-channel and p-channel CMOS switching transistors, respectively, the drain terminals of which are coupled to first and second output terminals, respectively. N-channel and p-channel shield transistors are connected in series between the first and second output terminals, and have their gate terminals coupled to the shield voltage.
摘要翻译：允许CMOS晶体管逻辑电路在更高的电源电压下工作，同时通过将每个输入信号提供为在两个不同电压范围内彼此跟踪的双输入信号来保持较低的电压处理几何形状。屏蔽电压近似位于最上面和最下面的电源电压之间的中间。第一输入信号在最低电源电压和屏蔽电压之间的范围内，第二输入信号在屏蔽电压和最上电源电压之间。第一和第二输入信号分别驱动n沟道和p沟道CMOS开关晶体管的栅极，漏极端分别耦合到第一和第二输出端。 N沟道和p沟道屏蔽晶体管串联连接在第一和第二输出端之间，并且其栅极端子耦合到屏蔽电压。

5. 发明授权

US5465054A High voltage CMOS logic using low voltage CMOS process 失效
标题翻译：高压CMOS逻辑采用低电压CMOS工艺
公开(公告)号：US5465054A
公开(公告)日：1995-11-07
申请号：US224762
申请日：1994-04-08
申请人： Richard A. Erhart
发明人： Richard A. Erhart
IPC分类号： H03K17/687 , G11C11/407 , G11C11/409 , H03K19/003 , H03K19/0948 , H03K17/10
CPC分类号： H03K19/00315
摘要： CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors before the gate terminals of each input switching transistor. Each shielding transistor has a gate terminal coupled to a shield voltage of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor, while preventing the gate of the switching transistor from rising above the shield voltage, in the case of n-channel devices, or below the shield voltage, in the case of p-channel devices. The source-drain channel of a p-channel output shielding transistor couples the output port of p-channel switching transistors to the gate output; the gate terminal of the such p-channel output shielding transistor is coupled to the shield voltage for preventing the drain of p-channel switching transistors from being pulled down below the shield voltage. A similar n-channel output shielding transistor couples the output port of n-channel switching transistors to the gate output for preventing the drain of n-channel switching transistors from being pulled above the shield voltage.
摘要翻译：允许CMOS晶体管逻辑电路在更高的电源电压下工作，同时通过在每个输入开关晶体管的栅极端子之前插入输入屏蔽晶体管来保持较低的电压处理几何形状。每个屏蔽晶体管具有栅极端子，其耦合到基本上在地电位和正电源电压之间的中间的幅度的屏蔽电压。输入信号由输入屏蔽晶体管的源极 - 漏极沟道传送到开关晶体管的栅极，同时在n沟道器件或以下的情况下，防止开关晶体管的栅极升高到屏蔽电压以上屏蔽电压，在p沟道器件的情况下。 p沟道输出屏蔽晶体管的源极 - 漏极沟道将p沟道开关晶体管的输出端口耦合到栅极输出; 这种p沟道输出屏蔽晶体管的栅极端子耦合到屏蔽电压，以防止p沟道开关晶体管的漏极被降低到屏蔽电压以下。类似的n沟道输出屏蔽晶体管将n沟道开关晶体管的输出端耦合到栅极输出，以防止n沟道开关晶体管的漏极被拉到屏蔽电压以上。

6. 发明授权

US5208833A Multi-level symbol synchronizer 失效
标题翻译：多级符号同步器
公开(公告)号：US5208833A
公开(公告)日：1993-05-04
申请号：US681841
申请日：1991-04-08
申请人： Richard A. Erhart , David F. Willard , James G. Mittel
发明人： Richard A. Erhart , David F. Willard , James G. Mittel
IPC分类号： H03L7/06 , H04L7/033 , H04L25/49 , H04L27/14
CPC分类号： H04L25/4917 , H04L7/0331
摘要： A symbol synchronizer for a communication receiver receiving multi-level data signals includes a reference clock generator for generating a reference clock signal having a predetermined time period, a state change detector for detecting state changes occurring within the received multi-level data signals over the predetermined time period to enable determining a time location corresponding to the detected state change wherein the time locations are assigned predetermined numeric values corresponding to the time locations determined, an accumulator for accumulating a time location for the time locations selected, and a phase adjusting circuit which is responsive to the time location count for adjusting the phase of the reference clock signal relative to the received multi-level data signal.
摘要翻译：用于接收多电平数据信号的通信接收机的符号同步器包括用于产生具有预定时间周期的参考时钟信号的参考时钟发生器，用于检测在所接收的多电平数据信号中发生的状态变化超过预定时间周期的状态变化检测器时间段，以使得能够确定对应于检测到的状态改变的时间位置，其中时间位置被分配与所确定的时间位置相对应的预定数值，累加器，用于累积所选择的时间位置的时间位置，以及相位调整电路，响应于时间位置计数，用于相对于所接收的多电平数据信号调整参考时钟信号的相位。

7. 发明授权

US5049875A Method and apparatus for out of range detection in response to nondetection of predetermined baud rates 失效
标题翻译：响应于预定波特率的非检测，超出范围检测的方法和装置
公开(公告)号：US5049875A
公开(公告)日：1991-09-17
申请号：US406489
申请日：1989-09-13
申请人： Joan S. DeLuca , Richard A. Erhart , Michael J. DeLuca
发明人： Joan S. DeLuca , Richard A. Erhart , Michael J. DeLuca
IPC分类号： G08B3/10 , H04W88/02
CPC分类号： H04W88/022 , G08B3/1066 , H04M1/72516
摘要： A baud rate detector determines the baud rates of signals received by a selective call receiver. If the signals have no detectable baud rate or the baud rate of the received signals does not match that of a plurality of known selective call network transmission baud rates, the selective call receiver indicates to its user that it is out of range of the network's transmitters.
摘要翻译：波特率检测器确定由选呼接收机接收的信号的波特率。如果信号没有可检测的波特率或接收到的信号的波特率与多个已知的选择呼叫网络传输波特率的波特率不匹配，则选呼接收机向用户指示它超出了网络发射机的范围。

8. 发明授权

US5381133A Selective call receiver with battery saving features and method therefor 失效
标题翻译：具有电池节省功能及其方法的选择性呼叫接收机
公开(公告)号：US5381133A
公开(公告)日：1995-01-10
申请号：US8124
申请日：1993-01-25
申请人： Richard A. Erhart , Renee Zuleta , David J. Hayes
发明人： Richard A. Erhart , Renee Zuleta , David J. Hayes
IPC分类号： H04W52/02 , H04W88/02 , H04Q7/00
CPC分类号： H04W52/0229 , H04W88/022
摘要： A selective call receiver (200) includes a receiver (204) receiving paging signals including a preamble, a synchronization codeword, and at least address information. A controller (206) controlling a supply of power to the receiver for receiving the paging signals. A synchronization obtaining circuitry (404, 406, 224), coupled to the receiver (204), obtains synchronization to the paging signal. The synchronization obtaining circuitry (404, 406, 224) includes a baud rate detector and synchronization codeword detector, coupled to the baud rate detector, detects the synchronization codeword. An address decoder, responsive to the synchronization codeword being detected, decodes the address information. A synchronization maintaining circuitry (404, 408, 224) maintains synchronization to the paging signals during address decoding. The synchronization maintaining circuitry (404, 408, 224) includes circuitry for enabling the power switch (210) which enables the receiver (204) for receiving the paging signals. The baud rate detector (224), responsive to the power being supplied to the receiver (204), detects baud rate during at least first (150) and second (152) portions of the address. A preamble detector (404), responsive to the second portion of the address being received, detects preamble during at least a portion of a second address (152).
摘要翻译：选呼接收机（200）包括接收包括前导码，同步码字和至少地址信息的寻呼信号的接收机（204）。控制器（206）控制向接收机供电以接收寻呼信号。耦合到接收器（204）的同步获取电路（404,406,224）获得与寻呼信号的同步。同步获取电路（404,406,224）包括耦合到波特率检测器的波特率检测器和同步码字检测器，检测同步码字。响应于所检测的同步码字的地址解码器对地址信息进行解码。在地址解码期间，同步维持电路（404,408,224）保持与寻呼信号的同步。同步维持电路（404,408,224）包括用于使电源开关（210）能够使接收器（204）接收寻呼信号的电路。波特率检测器（224）响应于提供给接收器（204）的功率，在地址的至少第一（150）和第二（152）部分期间检测波特率。响应于所接收的地址的第二部分的前导码检测器（404）在第二地址（152）的至少一部分期间检测前导码。

9. 发明授权

US5051999A Programmable error correcting apparatus within a paging receiver 失效
标题翻译：寻呼机内的可编程纠错装置
公开(公告)号：US5051999A
公开(公告)日：1991-09-24
申请号：US322437
申请日：1989-03-13
申请人： Richard A. Erhart , Joan S. DeLuca , Kevin T. McLaughlin
发明人： Richard A. Erhart , Joan S. DeLuca , Kevin T. McLaughlin
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15 , H04L1/00 , H04Q7/16
CPC分类号： H03M13/15
摘要： A paging receiver receiving message information having one of a plurality of (BCH) code word structures has a programmable error correcting apparatus for correcting bit errors within the message information. The programmable error correcting apparatus may be configured in response to identifying a signalling system and the code word structure corresponding to ther signalling system, or in response to changes in the code word structure within the message. A simplified error correcting apparatus may correct a single bit error within a code word structure. The programamble error correcting apparatus is capable of correcting any two bit error combination within the code word structure and contains sequential and combinational logic circuits. The programmable error correcting apparatus is integrated together with a microprocessor on a monolithic integrated circuit.
摘要翻译：接收具有多个（BCH）码字结构之一的消息信息的寻呼接收机具有用于校正消息信息内的位错误的可编程错误校正装置。可编程错误校正装置可以被配置为响应于识别信令系统和对应于其信令系统的代码字结构，或响应于消息内的代码字结构的变化。简化的纠错装置可以纠正码字结构内的单个位错误。编程码错误校正装置能够校正码字结构内的任何两位误差组合，并包含顺序和组合逻辑电路。可编程错误校正装置与单片集成电路上的微处理器集成在一起。

10. 发明申请

US20140333328A1 Apparatus and Method for TFT Fingerprint Sensor 审中-公开
标题翻译： TFT指纹传感器的设备和方法
公开(公告)号：US20140333328A1
公开(公告)日：2014-11-13
申请号：US14244534
申请日：2014-04-03
申请人： Richard B. Nelson , Richard A. Erhart
发明人： Richard B. Nelson , Richard A. Erhart
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/041 , G06F3/0416 , G06K9/0002
摘要： A low cost, two-dimensional, fingerprint sensor includes a pixel array, each pixel including a switch and a pixel electrode for forming a capacitance with a fingertip. One or more active transmission electrodes are spaced from a selected row of the pixel array, and transmit a carrier signal into the finger without direct coupling into the selected pixels. Signals sensed by the pixel array are coupled to an independent integrated circuit, and connections between the IC and the pixel array are reduced by demultiplexing row select lines, and by multiplexing sensed column data. Differential sensing may be used to improve common mode noise rejection. The fingerprint sensor may be conveniently incorporated within a conventional touchpad LCD panel, and can mimic the performance of lower density touchpad pixels.
摘要翻译：低成本的二维指纹传感器包括像素阵列，每个像素包括用于用指尖形成电容的开关和像素电极。一个或多个有源传输电极与所选择的像素阵列相隔开，并且将载波信号发射到手指中，而不直接耦合到所选择的像素中。由像素阵列感测的信号被耦合到独立的集成电路，并且通过解复用行选择线以及通过复用感测的列数据来减小IC和像素阵列之间的连接。差分感测可用于改善共模噪声抑制。指纹传感器可以方便地结合在常规的触摸板LCD面板中，并且可以模仿低密度触摸板像素的性能。

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