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1. 发明申请

US20050064635A1 METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR THIN SPACER FETs 有权
标题翻译：用于减少用于稀薄间隔FET的预硅氧烷清洁剂下的氧化物沉积的方法
公开(公告)号：US20050064635A1
公开(公告)日：2005-03-24
申请号：US10605311
申请日：2003-09-22
申请人： Atul Ajmera , Andres Bryant , Percy Gilbert , Michael Gribelyuk , Edward Maciejewski , Renee Mo , Shreesh Narasimha
发明人： Atul Ajmera , Andres Bryant , Percy Gilbert , Michael Gribelyuk , Edward Maciejewski , Renee Mo , Shreesh Narasimha
IPC分类号： H01L21/28 , H01L21/311 , H01L21/3205 , H01L21/336 , H01L21/8238 , H01L23/52 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/94
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.
摘要翻译：描述了在预硅化物清洁步骤期间以避免电介质层底切的方式形成CMOS器件的方法。在形成包括半导体衬底表面上的栅极堆叠的CMOS器件的情况下，图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，在衬底表面之上和之上形成介电层。在每个垂直侧壁处形成覆盖在电介质层上的各种氮化物间隔元件。使用蚀刻工艺去除衬底表面上的电介质层，使得保留每个间隔物下面的介电层的一部分。然后，在整个样品（栅极堆叠，每个栅极侧壁和衬底表面处的间隔元件）上沉积氮化物层，然后通过蚀刻工艺去除，使得仅一部分所述氮化物膜（“插塞”）遗迹。插头密封并封装每个所述间隔件下面的电介质层，从而防止在随后的硅化物前处理过程中电介质材料被切削。通过防止底切，本发明还防止蚀刻停止膜（在接触形成之前沉积）与栅极氧化物接触。因此，能够实现提高晶体管驱动电流所需的薄间隔晶体管几何形状的集成。

2. 发明申请

US20060057797A1 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
公开(公告)号：US20060057797A1
公开(公告)日：2006-03-16
申请号：US11266855
申请日：2005-11-04
申请人： Atul Ajmera , Andres Bryant , Percy Gilbert , Michael Gribelyuk , Edward Maciejewski , Renee Mo , Shreesh Narasimha
发明人： Atul Ajmera , Andres Bryant , Percy Gilbert , Michael Gribelyuk , Edward Maciejewski , Renee Mo , Shreesh Narasimha
IPC分类号： H01L21/8238
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

3. 发明申请

US20050277263A1 Forming Shallow Trench Isolation Without the Use of CMP 失效
标题翻译：形成浅沟槽隔离而不使用CMP
公开(公告)号：US20050277263A1
公开(公告)日：2005-12-15
申请号：US10710001
申请日：2004-06-11
申请人： Renee Mo , Shreesh Narasimha
发明人： Renee Mo , Shreesh Narasimha
IPC分类号： H01L21/331 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76283
摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.
摘要翻译：通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

4. 发明授权

US09184301B2 Planar and nanowire field effect transistors 有权
标题翻译：平面和纳米线场效应晶体管
公开(公告)号：US09184301B2
公开(公告)日：2015-11-10
申请号：US13600598
申请日：2012-08-31
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L29/786 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/423
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
摘要翻译：集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。

5. 发明申请

US20130221328A1 Pad-Less Gate-All Around Semiconductor Nanowire FETs On Bulk Semiconductor Wafers 有权
标题翻译：无衬底栅极 - 全周围半导体纳米线FET在散装半导体晶片上
公开(公告)号：US20130221328A1
公开(公告)日：2013-08-29
申请号：US13405732
申请日：2012-02-27
申请人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
发明人： Jeffrey W. Sleight , Josephine B. Chang , Isaac Lauer , Shreesh Narasimha
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/762
摘要： A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，该方法包括在半导体衬底上形成悬浮的纳米线，在纳米线的一部分周围形成栅极结构，形成邻近栅极的侧壁和周围部分的保护隔离层的纳米线从栅极延伸，去除未被间隔物结构保护的纳米线的暴露部分，以及在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成源极区域和漏极区域。

6. 发明申请

US20120319084A1 PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS 有权
标题翻译：平面和纳米级场效应晶体管
公开(公告)号：US20120319084A1
公开(公告)日：2012-12-20
申请号：US13600598
申请日：2012-08-31
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L27/088
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
摘要翻译：集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。

7. 发明授权

US08232599B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08232599B2
公开(公告)日：2012-07-31
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

8. 发明申请

US20120187492A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20120187492A1
公开(公告)日：2012-07-26
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

9. 发明申请

US20120180010A1 METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE 有权
标题翻译：使用低温退火工艺制造器件的方法，器件和设计结构
公开(公告)号：US20120180010A1
公开(公告)日：2012-07-12
申请号：US13421400
申请日：2012-03-15
申请人： Anthony G. DOMENICUCCI , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
发明人： Anthony G. DOMENICUCCI , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/324 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
摘要翻译：提供了使用退火处理序列制造器件的方法。更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

10. 发明申请

US20110225562A1 COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE 有权
标题翻译：用于PC路面平台的简化模型方法对设备性能的影响
公开(公告)号：US20110225562A1
公开(公告)日：2011-09-15
申请号：US13100584
申请日：2011-05-04
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F9/455
CPC分类号： G06F17/5036
摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature.
摘要翻译：一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。然后，晶体管紧凑型模型中的晶体管模型参数值被更新为晶体管器件，以包括要添加到内置deltaW值的ΔW加法器值。在设备仿真中使用的网表可以包括deltaW加法器值，以量化着陆垫特征的光刻舍入效应的影响。

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