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1. 发明授权

US07517768B2 Method for fabricating a heterojunction bipolar transistor 有权
标题翻译：异质结双极晶体管的制造方法
公开(公告)号：US07517768B2
公开(公告)日：2009-04-14
申请号：US10404781
申请日：2003-03-31
申请人： Ravindra Soman , Anand Murthy , Peter VanDerVoorn , Shahriar Ahmed
发明人： Ravindra Soman , Anand Murthy , Peter VanDerVoorn , Shahriar Ahmed
IPC分类号： H01L21/331
CPC分类号： H01L29/66242
摘要： A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.
摘要翻译：具有SiGe：C膜的双极晶体管和形成在SiGe：C薄膜下面的晶种层及其制造方法。该方法包括将基板放置在反应器室中并将硅源气体引入反应器室以形成硅籽晶层。反应室保持在低于45托的压力和约700℃至850℃之间的温度。形成种子层之后，停止硅源气体。然后将反应器室同时调节至约70托和90托之间的压力以及约600℃和650℃之间的温度。引入硅源气体，锗源气体和碳源气体以形成种子层上的SiGe：C膜。

2. 发明授权

US07005359B2 Bipolar junction transistor with improved extrinsic base region and method of fabrication 失效
标题翻译：具有改进的外在基极区域的双极结晶体管及其制造方法
公开(公告)号：US07005359B2
公开(公告)日：2006-02-28
申请号：US10715971
申请日：2003-11-17
申请人： Shahriar Ahmed , Ravindra Soman , Anand Murthy , Mark Bohr
发明人： Shahriar Ahmed , Ravindra Soman , Anand Murthy , Mark Bohr
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L29/42304 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
摘要翻译：描述了双极晶体管及其制造。通过在第一外延层上生长第二更重掺杂的外延层来形成非本征基区。第二层在覆盖多晶硅发射器基座的下方延伸并与其绝缘。

3. 发明申请

US20060113634A1 Bipolar junction transistor with improved extrinsic base region and method of fabrication 审中-公开
公开(公告)号：US20060113634A1
公开(公告)日：2006-06-01
申请号：US11269477
申请日：2005-11-07
申请人： Shahriar Ahmed , Ravindra Soman , Anand Murthy , Mark Bohr
发明人： Shahriar Ahmed , Ravindra Soman , Anand Murthy , Mark Bohr
IPC分类号： H01L29/70
CPC分类号： H01L29/66287 , H01L29/42304 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

4. 发明申请

US20050104160A1 Bipolar junction transistor with improved extrinsic base region and method of fabrication 失效
标题翻译：具有改进的外在基极区域的双极结晶体管及其制造方法
公开(公告)号：US20050104160A1
公开(公告)日：2005-05-19
申请号：US10715971
申请日：2003-11-17
申请人： Shahriar Ahmed , Ravindra Soman , Anand Murthy , Mark Bohr
发明人： Shahriar Ahmed , Ravindra Soman , Anand Murthy , Mark Bohr
IPC分类号： H01L21/331 , H01L29/423 , H01L29/732 , H01L29/737 , H01L21/8222 , H01L27/082 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66287 , H01L29/42304 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
摘要翻译：描述了双极晶体管及其制造。通过在第一外延层上生长第二更重掺杂的外延层来形成非本征基区。第二层在覆盖多晶硅发射器基座的下方延伸并与其绝缘。

5. 发明授权

US06579771B1 Self aligned compact bipolar junction transistor layout, and method of making same 有权
标题翻译：自对准紧凑型双极结晶体管布局及其制造方法
公开(公告)号：US06579771B1
公开(公告)日：2003-06-17
申请号：US10013225
申请日：2001-12-10
申请人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
发明人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
IPC分类号： H01L218228
CPC分类号： H01L29/66287
摘要： The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.
摘要翻译：本发明涉及一种形成双极结型晶体管（BJT）的方法，其包括在衬底上形成拓扑结构。此后，在拓扑形成间隔物。基底层由间隔物上方的外延硅和拓扑形成。通过从间隔物的扩散形成在衬底中的泄漏块结构。此后，BJT完成了基层和隔离层。

6. 发明授权

US07064042B1 Self aligned compact bipolar junction transistor layout, and method of making same 失效
公开(公告)号：US07064042B1
公开(公告)日：2006-06-20
申请号：US10877749
申请日：2004-06-24
申请人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
发明人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/732
摘要： The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

7. 发明授权

US07202514B2 Self aligned compact bipolar junction transistor layout and method of making same 有权
标题翻译：自对准紧凑型双极结晶体管布局及其制作方法
公开(公告)号：US07202514B2
公开(公告)日：2007-04-10
申请号：US10418395
申请日：2003-04-17
申请人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
发明人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green , Anand Murthy
IPC分类号： H01L31/072
CPC分类号： H01L29/66287
摘要： The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.
摘要翻译：本发明涉及一种形成双极结型晶体管（BJT）的方法，其包括在衬底上形成拓扑结构。此后，在拓扑形成间隔物。基底层由间隔物上方的外延硅和拓扑形成。通过从间隔物的扩散形成在衬底中的泄漏块结构。此后，BJT完成了基层和隔离层。

8. 发明授权

US06703685B2 Super self-aligned collector device for mono-and hetero bipolar junction transistors 有权
标题翻译：用于单和双极结型晶体管的超自对准集电极器件
公开(公告)号：US06703685B2
公开(公告)日：2004-03-09
申请号：US10013075
申请日：2001-12-10
申请人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green
发明人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/0821
摘要： The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.
摘要翻译：本发明涉及一种形成紧凑型双极结型晶体管（BJT）的方法，其包括形成邻近发射极堆叠的自对准集电极阱和隔离结构。基底层由设置在基板中的外延硅形成。

9. 发明申请

US20090241075A1 TEST CHIP VALIDATION AND DEVELOPMENT SYSTEM 审中-公开
标题翻译：测试芯片验证和开发系统
公开(公告)号：US20090241075A1
公开(公告)日：2009-09-24
申请号：US12053852
申请日：2008-03-24
申请人： Shahriar Ahmed , Kedar Dongre , Jeffrey C. Hunter , Rott Pavel , Vincent Rayappa , Joseph Yip
发明人： Shahriar Ahmed , Kedar Dongre , Jeffrey C. Hunter , Rott Pavel , Vincent Rayappa , Joseph Yip
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/12 , G06F2217/14 , Y02P90/265
摘要： Embodiments of an IC design system for test row/structure layout design are described in this application. The design system may include a test chip complier database, a test chip complier engine (TCCE), and a user interface module. The TCCE may be configured to communicate with at least the test chip compiler database and the user interface module, and configured to allow a user to automatically generate a test chip layout by providing an integrated circuit design system. With the system, a user can automatically generate a design by specifying the test row or test structure layout requirements for the design using sets of predefined templates, changing design template parameters using a table driven input format, scheduling generation of the design on a preferred layout design tool, visually inspecting the generated design for errors, and/or applying version controls to the generated design. Other embodiments are described.
摘要翻译：在本申请中描述了用于测试行/结构布局设计的IC设计系统的实施例。该设计系统可以包括测试芯片编码器数据库，测试芯片编译器引擎（TCCE）和用户接口模块。 TCCE可以被配置为与至少测试芯片编译器数据库和用户界面模块通信，并且被配置为允许用户通过提供集成电路设计系统来自动生成测试芯片布局。使用该系统，用户可以通过使用预定义模板集来指定设计的测试行或测试结构布局要求来自动生成设计，使用表驱动的输入格式更改设计模板参数，在优选布局上调度生成设计设计工具，目视检查生成的设计错误，和/或对生成的设计应用版本控制。描述其他实施例。

10. 发明授权

US07414298B2 Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same 有权
标题翻译：用于单和双极结型晶体管的超自对准集电极器件及其制造方法
公开(公告)号：US07414298B2
公开(公告)日：2008-08-19
申请号：US10633055
申请日：2003-07-31
申请人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green
发明人： Shahriar Ahmed , Mark Bohr , Stephen Chambers , Richard Green
IPC分类号： H01L29/06
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/0821
摘要： The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.
摘要翻译：本发明涉及一种形成紧凑型双极结型晶体管（BJT）的方法，其包括形成邻近发射极堆叠的自对准集电极阱和隔离结构。基底层由设置在基板中的外延硅形成。

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