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1. 发明授权

US06358855B1 Clean method for recessed conductive barriers 有权
标题翻译：凹陷导电屏障的清洁方法
公开(公告)号：US06358855B1
公开(公告)日：2002-03-19
申请号：US09595795
申请日：2000-06-16
申请人： Ravikumar Ramachandran , Nicolas Nagel , Christopher C. Parks
发明人： Ravikumar Ramachandran , Nicolas Nagel , Christopher C. Parks
IPC分类号： H01L21302
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76861 , H01L21/7687 , H01L27/10855
摘要： A method for cleaning an oxidized diffusion barrier layer, in accordance with the present invention, includes providing a conductive diffusion barrier layer employed for preventing oxygen and metal diffusion therethrough and providing a wet chemical etchant including hydrofluoric acid. The diffusion barrier layer is etched with the wet chemical etchant to remove oxides from the diffusion barrier layer such that by employing the wet chemical etchant linear electrical behavior is achieved through the diffusion barrier layer.
摘要翻译：根据本发明的用于清洁氧化扩散阻挡层的方法包括提供用于防止氧和金属扩散的导电扩散阻挡层，并提供包括氢氟酸在内的湿化学蚀刻剂。用湿化学蚀刻剂蚀刻扩散阻挡层以从扩散阻挡层去除氧化物，使得通过使用湿化学蚀刻剂，通过扩散阻挡层实现线性电性能。

2. 发明授权

US07462038B2 Interconnection structure and method of manufacturing the same 有权
标题翻译：互连结构及制造方法
公开(公告)号：US07462038B2
公开(公告)日：2008-12-09
申请号：US11676622
申请日：2007-02-20
申请人： Roman Knoefler , Christoph Kleint , Steffen Meyer , Nicolas Nagel
发明人： Roman Knoefler , Christoph Kleint , Steffen Meyer , Nicolas Nagel
IPC分类号： H01R12/00
CPC分类号： H01R13/22
摘要： An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.
摘要翻译：互连结构包括具有均匀间隔的接触的两个交错的接触排。每个接触排沿第一方向延伸。互连结构还包括沿着与第一方向相交的第二方向延伸的导电线。互连结构还包括中间触点，其中每个中间触点与触点之一和导线中的一个接触。

3. 发明授权

US07416976B2 Method of forming contacts using auxiliary structures 有权
标题翻译：使用辅助结构形成触点的方法
公开(公告)号：US07416976B2
公开(公告)日：2008-08-26
申请号：US11217122
申请日：2005-08-31
申请人： Josef Willer , Patrick Haibach , Christoph Andreas Kleint , Nicolas Nagel
发明人： Josef Willer , Patrick Haibach , Christoph Andreas Kleint , Nicolas Nagel
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.
摘要翻译：半导体产品包括具有基板表面的基板。多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。在字线之间提供多个导电接触结构。该产品还包括多个填充结构。每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。两个相应的接触结构在第一方向上彼此间隔一定距离。在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

4. 发明授权

US07319270B2 Multi-layer electrode and method of forming the same 有权
标题翻译：多层电极及其形成方法
公开(公告)号：US07319270B2
公开(公告)日：2008-01-15
申请号：US10929157
申请日：2004-08-30
申请人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Michael Wise
发明人： Jingyu Lian , Chenting Lin , Nicolas Nagel , Michael Wise
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/74
CPC分类号： H01L28/75 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , Y10S257/906 , Y10S257/908
摘要： An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.
摘要翻译：互连包括形成在电介质层中的开口。导电屏障沉积在开口中，在其上沉积第一导电层。导电氧化物沉积在第一导电层之上，并且由与第一导电层相同的材料形成的第二导电层沉积在导电衬垫上。

5. 发明申请

US20080009115A1 Method of manufacturing at least one semiconductor component and memory cells 有权
标题翻译：制造至少一个半导体部件和存储单元的方法
公开(公告)号：US20080009115A1
公开(公告)日：2008-01-10
申请号：US11483968
申请日：2006-07-10
申请人： Josef Willer , Nicolas Nagel
发明人： Josef Willer , Nicolas Nagel
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/792
摘要： A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.
摘要翻译：公开了制造至少一个NAND耦合的半导体部件的方法。在半导体衬底上或上方形成层结构。图案化层结构以暴露待掺杂的至少一个区域。曝光区域被掺杂并退火。图案化层结构至少部分地被去除。在去除图案层结构的区域中形成更换材料，从而形成至少一个NAND耦合的半导体部件。

6. 发明申请

US20070001305A1 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070001305A1
公开(公告)日：2007-01-04
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

7. 发明申请

US20060286796A1 Method of forming a contact in a flash memory device 有权
标题翻译：在闪速存储器件中形成触点的方法
公开(公告)号：US20060286796A1
公开(公告)日：2006-12-21
申请号：US11157143
申请日：2005-06-20
申请人： Nicolas Nagel , Dominik Olligs
发明人： Nicolas Nagel , Dominik Olligs
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.
摘要翻译：在闪速存储器件中形成位线和局部互连之间的接触的方法包括在沉积氧化物介电层之前在平坦化表面上形成硬掩模层，其包括局部互连的暴露的顶部部分。硬掩模层可以由与层间电介质材料（例如氮化物）相比具有耐蚀刻性的材料构成。硬掩模中的开口定义了与顶部暴露的局部互连的触点的位置。

8. 发明申请

US20060151819A1 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US20060151819A1
公开(公告)日：2006-07-13
申请号：US11373080
申请日：2006-03-09
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬层，并且蚀刻用于V0接触的孔，直到蚀刻被衬垫层停止。

9. 发明申请

US20050045932A1 Process for fabrication of a ferroelectric capacitor 失效
标题翻译：铁电电容器制造工艺
公开(公告)号：US20050045932A1
公开(公告)日：2005-03-03
申请号：US10651614
申请日：2003-08-29
申请人： Karl Hornik , Rainer Bruchhaus , Nicolas Nagel
发明人： Karl Hornik , Rainer Bruchhaus , Nicolas Nagel
IPC分类号： H01L21/02 , H01L21/316 , H01L21/00 , H01L29/76
CPC分类号： H01L28/56 , H01L21/31616 , H01L21/31683
摘要： A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Ti 5 over an insulating layer 3 of Al2O3, and oxidising the Ti layer to form a TiO2 layer 7. Subsequently, a layer of PZT 9 is formed over the TiO2 layer 7. The PZT layer 9 is subjected to an annealing step in which, due to the presence of the TiO2 layer 7 it crystallises to form a layer 11 with a high degree of (111)-texture.
摘要翻译：一种用于制造铁电电容器的方法，包括在Al 2 O 3的绝缘层3上沉积Ti 5层，并氧化Ti层以形成TiO 2层7.随后，在TiO 2层7上形成一层PZT 9 对PZT层9进行退火处理，其中由于TiO 2层7的存在，其结晶以形成具有高度（111） - 纹理的层11。

10. 发明申请

US20050013091A1 MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS 有权
标题翻译：多层障碍物允许用于电容电容器的恢复电极
公开(公告)号：US20050013091A1
公开(公告)日：2005-01-20
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

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