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1. 发明授权

US07521351B2 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US07521351B2
公开(公告)日：2009-04-21
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

2. 发明申请

US20070077748A1 Method for forming a semiconductor product and semiconductor product 审中-公开
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070077748A1
公开(公告)日：2007-04-05
申请号：US11241877
申请日：2005-09-30
申请人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
发明人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
IPC分类号： H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76838 , H01L27/11521 , H01L27/11568
摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).
摘要翻译：半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

3. 发明授权

US08009477B2 Integrated circuit and method of forming an integrated circuit 有权
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US08009477B2
公开(公告)日：2011-08-30
申请号：US12182714
申请日：2008-07-30
申请人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
发明人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
IPC分类号： G11C11/40 , H01L27/088 , H01L29/78 , H01L21/4763
CPC分类号： G11C5/063 , H01L21/76804 , H01L21/76807 , H01L21/76813
摘要： An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.
摘要翻译：集成电路和形成集成电路的方法。一个实施例包括形成在载体的表面上方的导线。在垂直于载体表面的方向上的导线的侧壁的斜面显示出不连续性，并且导电线的上部的宽度大于下部的对应宽度。

4. 发明授权

US07935608B2 Storage cell having a T-shaped gate electrode and method for manufacturing the same 有权
标题翻译：具有T形栅电极的存储单元及其制造方法
公开(公告)号：US07935608B2
公开(公告)日：2011-05-03
申请号：US12131794
申请日：2008-06-02
申请人： Frank Heinrichsdorff , Nicolas Nagel , Jens-Uwe Sachse , Andreas Voerckel , Dominik Olligs , Torsten Mueller
发明人： Frank Heinrichsdorff , Nicolas Nagel , Jens-Uwe Sachse , Andreas Voerckel , Dominik Olligs , Torsten Mueller
IPC分类号： H01L21/76
CPC分类号： H01L27/1203 , H01L21/28273 , H01L21/84 , H01L27/11517 , H01L29/66825 , H01L29/7881
摘要： A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.
摘要翻译：提供了一种用于制造包括至少一个存储单元的集成电路的方法。该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。

5. 发明申请

US20090294825A1 STORAGE CELL HAVING A T-SHAPED GATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：具有T形门电极的存储单元及其制造方法
公开(公告)号：US20090294825A1
公开(公告)日：2009-12-03
申请号：US12131794
申请日：2008-06-02
申请人： Frank Heinrichsdorff , Nicolas Nagel , Jens-Uwe Sachse , Andreas Voerckel , Dominik Olligs , Torsten Mueller
发明人： Frank Heinrichsdorff , Nicolas Nagel , Jens-Uwe Sachse , Andreas Voerckel , Dominik Olligs , Torsten Mueller
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/28273 , H01L21/84 , H01L27/11517 , H01L29/66825 , H01L29/7881
摘要： A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.
摘要翻译：提供了一种用于制造包括至少一个存储单元的集成电路的方法。该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。

6. 发明申请

US20070001305A1 Method for forming a semiconductor product and semiconductor product 失效
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070001305A1
公开(公告)日：2007-01-04
申请号：US11172366
申请日：2005-06-30
申请人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
发明人： Thomas Mikolajick , Torsten Mueller , Nicolas Nagel , Lars Bach , Dominik Olligs , Veronika Polei
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L27/115 , H01L27/11568
摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.
摘要翻译：半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。在其中设置有具有接触孔的第二介质层。接触孔在第一横向具有宽度。该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

7. 发明申请

US20060286796A1 Method of forming a contact in a flash memory device 有权
标题翻译：在闪速存储器件中形成触点的方法
公开(公告)号：US20060286796A1
公开(公告)日：2006-12-21
申请号：US11157143
申请日：2005-06-20
申请人： Nicolas Nagel , Dominik Olligs
发明人： Nicolas Nagel , Dominik Olligs
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.
摘要翻译：在闪速存储器件中形成位线和局部互连之间的接触的方法包括在沉积氧化物介电层之前在平坦化表面上形成硬掩模层，其包括局部互连的暴露的顶部部分。硬掩模层可以由与层间电介质材料（例如氮化物）相比具有耐蚀刻性的材料构成。硬掩模中的开口定义了与顶部暴露的局部互连的触点的位置。

8. 发明申请

US20100027311A1 INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US20100027311A1
公开(公告)日：2010-02-04
申请号：US12182714
申请日：2008-07-30
申请人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
发明人： Christoph Kleint , Nicolas Nagel , Dominik Olligs , Matthias Markert
IPC分类号： H01L21/768 , G11C5/06
CPC分类号： G11C5/063 , H01L21/76804 , H01L21/76807 , H01L21/76813
摘要： An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.
摘要翻译：集成电路和形成集成电路的方法。一个实施例包括形成在载体的表面上方的导线。在垂直于载体表面的方向上的导线的侧壁的斜面显示出不连续性，并且导电线的上部的宽度大于下部的对应宽度。

9. 发明授权

US07320934B2 Method of forming a contact in a flash memory device 有权
标题翻译：在闪速存储器件中形成触点的方法
公开(公告)号：US07320934B2
公开(公告)日：2008-01-22
申请号：US11157143
申请日：2005-06-20
申请人： Nicolas Nagel , Dominik Olligs
发明人： Nicolas Nagel , Dominik Olligs
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/76802 , H01L21/76895 , H01L27/11568
摘要： A method of forming a contact between a bitline and a local interconnect in a flash memory device comprises forming a hard mask layer on a planarized surface that includes an exposed top section of the local interconnects prior to depositing an oxide dielectric layer. The hard mask layer may be composed of a material that has an etch resistance as compared to the interlayer dielectric material, e.g., nitride. Openings in the hard mask define positions for the contacts to the local interconnects exposed in the top section.
摘要翻译：在闪速存储器件中形成位线和局部互连之间的接触的方法包括在沉积氧化物介电层之前在平坦化表面上形成硬掩模层，其包括局部互连的暴露的顶部部分。硬掩模层可以由与层间电介质材料（例如氮化物）相比具有耐蚀刻性的材料构成。硬掩模中的开口定义了与顶部暴露的局部互连的触点的位置。

10. 发明授权

US07642158B2 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07642158B2
公开(公告)日：2010-01-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

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