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    • 3. 发明授权
    • Prioritizing and locking removed and subsequently reloaded cache lines
    • 移除优先级和锁定,随后重新加载高速缓存行
    • US06901483B2
    • 2005-05-31
    • US10279246
    • 2002-10-24
    • John T. RobinsonRobert B. TremaineMichael E. Wazlowski
    • John T. RobinsonRobert B. TremaineMichael E. Wazlowski
    • G06F12/00G06F12/12
    • G06F12/126
    • A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special treatment to the reloading of a line that has been recently cast out. A line which has been reloaded after having been recently cast out is assigned a special encoding which temporarily gives priority to the line in the cache so that it will not be selected for replacement in the usual least recently used replacement process. This method of line selection for replacement improves system performance by providing better hit rates in the cache hierarchy levels above, by ensuring that heavily used lines in the levels above are not aged out of the levels below due to lack of use.
    • 一种用于在包含集合关联高速缓存存储器系统中选择要替代的方法,该系统基于最近最近使用的替换策略,但是被增强以检测并对最近被抛出的行的重新加载进行特殊处理。 在最近被淘汰之后重新加载的行被分配一个专门的编码,它暂时优先地将高速缓存中的行优先,以便在通常的最近最近使用的替换过程中不被选择进行替换。 这种替代选线方法通过在上述缓存层次结构中提供更好的命中率来提高系统性能,通过确保上述级别中的使用过多的线路由于缺乏使用而不会超出以下级别。
    • 5. 发明授权
    • (146,130) error correction code utilizing address information
    • (146,130)利用地址信息的纠错码
    • US06751769B2
    • 2004-06-15
    • US10349992
    • 2003-01-23
    • Chin-Long ChenR. Brett TremaineMichael E. Wazlowski
    • Chin-Long ChenR. Brett TremaineMichael E. Wazlowski
    • G11C2900
    • G11C7/24G06F11/1016G11C7/1006
    • A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.
    • 一种在例如从存储器阵列到存储器控制器的计算机系统中发送的数据流中检测双符号错误和校正单符号错误的方法。 该方法包括对使用逻辑电路进行编码的数据流进行解码,逻辑电路具有作为输入的数据作为输入,以及从数据的系统地址导出的两个地址奇偶校验位。 可以通过该代码检测从错误地址检索的数据。 逻辑电路由包括128个数据位,16个校验位和2个地址奇偶校验位的(146,130)码的奇偶校验矩阵描述。 虽然代码的符号宽度是4位,但代码也可以有效地用于存储器芯片宽度为8位的存储器系统中。