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1. 发明授权

US06462394B1 Device configured to avoid threshold voltage shift in a dielectric film 失效
标题翻译：器件被配置为避免电介质膜中的阈值电压偏移
公开(公告)号：US06462394B1
公开(公告)日：2002-10-08
申请号：US09312373
申请日：1999-05-13
申请人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L2900
CPC分类号： H01L23/564 , H01L21/3144 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

2. 发明授权

US07067442B1 Method to avoid threshold voltage shift in thicker dielectric films 失效
标题翻译：避免较厚介质膜中阈值电压漂移的方法
公开(公告)号：US07067442B1
公开(公告)日：2006-06-27
申请号：US09654093
申请日：2000-08-31
申请人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P. S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L21/31
CPC分类号： H01L23/3171 , H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/3162 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

3. 发明授权

US08202806B2 Method to avoid threshold voltage shift in thicker dielectric films 失效
标题翻译：避免较厚介质膜中阈值电压漂移的方法
公开(公告)号：US08202806B2
公开(公告)日：2012-06-19
申请号：US11242375
申请日：2005-10-03
申请人： Randhir P.S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P.S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/3171 , H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/3162 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

4. 发明申请

US20060030162A1 Method to avoid threshold voltage shift in thicker dielectric films 失效
公开(公告)号：US20060030162A1
公开(公告)日：2006-02-09
申请号：US11242375
申请日：2005-10-03
申请人： Randhir Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L21/469
CPC分类号： H01L23/3171 , H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/3162 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

5. 发明授权

US07750382B2 Image sensor having a charge storage region provided within an implant region 有权
标题翻译：具有设置在植入区域内的电荷存储区域的图像传感器
公开(公告)号：US07750382B2
公开(公告)日：2010-07-06
申请号：US12324083
申请日：2008-11-26
申请人： Howard Rhodes
发明人： Howard Rhodes
IPC分类号： H01L31/062
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689 , H01L31/035272
摘要： A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.
摘要翻译：公开了一种位于像素传感器单元的晶体管阵列下方并且与像素传感器单元的第二导电类型的光电二极管的掺杂区相邻的第一导电类型的深度注入区域。深注入区域减小了表面泄漏和暗电流，并且通过在第二导电类型的光电二极管的掺杂区域中作为光生电荷的反射阻挡来增加光电二极管的电容。深注入区域还提供从光电二极管的电荷收集区域到与传输晶体管的栅极相邻的浮动扩散区域的改进的电荷转移。

6. 发明申请

US20090179296A1 CMOS IMAGER PIXEL DESIGNS 审中-公开
标题翻译： CMOS IMAGER像素设计
公开(公告)号：US20090179296A1
公开(公告)日：2009-07-16
申请号：US12349968
申请日：2009-01-07
申请人： Howard Rhodes , Jeff McKee
发明人： Howard Rhodes , Jeff McKee
IPC分类号： H01L31/0256
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609
摘要： A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.
摘要翻译：公开了连接到CMOS成像器的各种光敏元件和/或电元件的电荷存储电容器以及形成方法。电荷存储电容器可以完全在CMOS成像器的场氧化物区域上形成，整个在像素传感器单元的有效区域上，或部分地在场氧化物区域上，部分地在像素传感器单元的有源像素区域上形成。

7. 发明申请

US20090078978A1 IMAGE SENSOR HAVING A CHARGE STORAGE REGION PROVIDED WITHIN AN IMPLANT REGION 有权
标题翻译：具有在一个植被区域内提供的充电储存区域的图像传感器
公开(公告)号：US20090078978A1
公开(公告)日：2009-03-26
申请号：US12324083
申请日：2008-11-26
申请人： Howard Rhodes
发明人： Howard Rhodes
IPC分类号： H01L27/146
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689 , H01L31/035272
摘要： A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.
摘要翻译：公开了一种位于像素传感器单元的晶体管阵列下方并且与像素传感器单元的第二导电类型的光电二极管的掺杂区相邻的第一导电类型的深度注入区域。深注入区域减小了表面泄漏和暗电流，并且通过在第二导电类型的光电二极管的掺杂区域中作为光生电荷的反射阻挡来增加光电二极管的电容。深注入区域还提供从光电二极管的电荷收集区域到与传输晶体管的栅极相邻的浮动扩散区域的改进的电荷转移。

8. 发明授权

US07470560B2 Image sensor having a charge storage region provided within an implant region 有权
标题翻译：具有设置在植入区域内的电荷存储区域的图像传感器
公开(公告)号：US07470560B2
公开(公告)日：2008-12-30
申请号：US11434767
申请日：2006-05-17
申请人： Howard Rhodes , Chandra Mouli
发明人： Howard Rhodes , Chandra Mouli
IPC分类号： H01L21/00
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689 , H01L31/035272
摘要： A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.
摘要翻译：公开了一种位于像素传感器单元的晶体管阵列下方并且与像素传感器单元的第二导电类型的光电二极管的掺杂区相邻的第一导电类型的深度注入区域。深注入区域减小了表面泄漏和暗电流，并且通过在第二导电类型的光电二极管的掺杂区域中作为光生电荷的反射阻挡来增加光电二极管的电容。深注入区域还提供从光电二极管的电荷收集区域到与传输晶体管的栅极相邻的浮动扩散区域的改进的电荷转移。

9. 发明授权

US07303938B2 Gated isolation structure for imagers 有权
标题翻译：成像仪的门控隔离结构
公开(公告)号：US07303938B2
公开(公告)日：2007-12-04
申请号：US10771290
申请日：2004-02-05
申请人： Chandra Mouli , Howard Rhodes
发明人： Chandra Mouli , Howard Rhodes
IPC分类号： H01L29/762 , H01L21/339
CPC分类号： H01L27/14609 , H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14689
摘要： Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.
摘要翻译：用于隔离图像传感器像素的像素的隔离方法和设备。隔离结构和方法包括在场隔离区域上形成偏置栅极并邻近图像传感器的像素。隔离方法还包括在场隔离区域的大部分上形成隔离栅极以隔离像素阵列中的像素。

10. 发明申请

US20070205447A1 Active pixel sensor with a diagonal active area 失效
标题翻译：有源像素传感器具有对角线活动区域
公开(公告)号：US20070205447A1
公开(公告)日：2007-09-06
申请号：US11797756
申请日：2007-05-07
申请人： Howard Rhodes
发明人： Howard Rhodes
IPC分类号： H01L31/062
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/376
摘要： An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.
摘要翻译：一种成像装置，其形成为具有连接到公共列线的行中的两个相邻像素的CMOS半导体集成电路。通过使行的相邻像素共享列线，CMOS成像器电路消除了允许制造较小成像器的传统成像器的一半列线。成像装置还可以被制造成具有对角线有源区域以促进两个相邻像素与单列线的接触，并允许线性行选择线，复位线和列线。

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