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1. 发明授权

US07273776B2 Methods of forming a P-well in an integrated circuit device 失效
标题翻译：在集成电路器件中形成P阱的方法
公开(公告)号：US07273776B2
公开(公告)日：2007-09-25
申请号：US10899596
申请日：2004-07-27
申请人： Ranadeep Dutta , Frank L. Thiel
发明人： Ranadeep Dutta , Frank L. Thiel
IPC分类号： H01L21/8238
CPC分类号： H01L29/66272 , H01L21/82285
摘要： The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped region in the first layer of epitaxial material, forming a second layer of epitaxial material above the first layer of epitaxial material, forming a second doped region in the second layer of epitaxial material, and performing at least one heat treating process.
摘要翻译：本发明一般涉及在集成电路器件中形成p阱的方法。在一个说明性实施例中，该方法包括在衬底的有源层上方形成外延材料的第一层，在第一外延材料层中形成第一掺杂区，在外延材料的第一层之上形成第二层外延材料在所述第二外延材料层中形成第二掺杂区，并进行至少一个热处理工艺。

2. 发明授权

US07253498B2 Bipolar transistor with geometry optimized for device performance, and method of making same 失效
标题翻译：具有针对器件性能优化的几何形状的双极晶体管及其制造方法
公开(公告)号：US07253498B2
公开(公告)日：2007-08-07
申请号：US10885250
申请日：2004-07-06
申请人： Ranadeep Dutta
发明人： Ranadeep Dutta
IPC分类号： H01L27/82
CPC分类号： H01L29/73 , H01L29/0692
摘要： The present invention is generally directed to bipolar transistors with geometry optimized for device performance and various methods of making same. In one illustrative embodiment, the device includes a substrate, an intrinsic base region formed in the substrate, a continuous emitter region formed within the intrinsic base region, the emitter region having a plurality of substantially hexagonal shaped openings defined therein, and a plurality of extrinsic base regions formed in the substrate, wherein each of the extrinsic base regions is positioned within an area defined by one of the plurality of substantially hexagonal shaped openings.
摘要翻译：本发明一般涉及具有针对器件性能优化的几何形状的双极晶体管及其制造方法。在一个说明性实施例中，器件包括衬底，形成在衬底中的本征基极区域，形成在本征基极区域内的连续发射极区域，发射极区域具有限定在其中的多个基本上六边形形状的开口，以及多个外部形成在基板中的基部区域，其中每个非本征基极区域位于由多个基本六边形形状的开口之一限定的区域内。

3. 发明申请

US20090170269A1 HIGH VOLTAGE MOSFET DEVICES CONTAINING TIP COMPENSATION IMPLANT 审中-公开
标题翻译：高压MOSFET器件包含提示补偿植入物
公开(公告)号：US20090170269A1
公开(公告)日：2009-07-02
申请号：US11968135
申请日：2007-12-31
申请人： Ranadeep Dutta
发明人： Ranadeep Dutta
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/7833
摘要： Semiconductor devices and methods for making semiconductor devices are described in this application. The semiconductor devices comprise a MOSFET device in a semiconductor substrate, with the MOSFET device containing source and drain regions with a tip implant region near the surface of the substrate. The tip implant region contains a tip compensation implant region located under the gate of the MOSFET device that overlaps with the source and drain. The tip compensation implant region reduces the dopant concentration in this gate-drain overlap region, while maintaining a graded drain-well junction profile, thereby reducing the band to band tunneling and increasing the drain breakdown voltage. Other embodiments are described.
摘要翻译：在本申请中描述了用于制造半导体器件的半导体器件和方法。半导体器件包括半导体衬底中的MOSFET器件，其中MOSFET器件包含在衬底表面附近具有尖端注入区的源区和漏区。尖端植入区域包含位于MOSFET器件的栅极下方的与源极和漏极重叠的尖端补偿注入区域。尖端补偿注入区域减小了该栅极 - 漏极重叠区域中的掺杂剂浓度，同时保持了梯度的漏 - 阱结结构，从而减小了带带隧穿和增加漏极击穿电压。描述其他实施例。

4. 发明授权

US07005702B1 IGBT with amorphous silicon transparent collector 有权
公开(公告)号：US07005702B1
公开(公告)日：2006-02-28
申请号：US09566219
申请日：2000-05-05
申请人： Richard Francis , Chiu Ng , Hamilton Lu , Ranadeep Dutta
发明人： Richard Francis , Chiu Ng , Hamilton Lu , Ranadeep Dutta
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66333 , H01L29/0834 , H01L29/7395
摘要： The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.

5. 发明申请

US20060094179A1 IGBT with amorphous silicon transparent collector 有权
公开(公告)号：US20060094179A1
公开(公告)日：2006-05-04
申请号：US11297571
申请日：2005-12-08
申请人： Richard Francis , Chiu Ng , Hamilton Lu , Ranadeep Dutta
发明人： Richard Francis , Chiu Ng , Hamilton Lu , Ranadeep Dutta
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/66333 , H01L29/0834 , H01L29/7395
摘要： The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.

6. 发明申请

US20060024927A1 Methods of forming a P-well in an integrated circuit device 失效
标题翻译：在集成电路器件中形成P阱的方法
公开(公告)号：US20060024927A1
公开(公告)日：2006-02-02
申请号：US10899596
申请日：2004-07-27
申请人： Ranadeep Dutta , Frank Thiel
发明人： Ranadeep Dutta , Frank Thiel
IPC分类号： H01L21/425
CPC分类号： H01L29/66272 , H01L21/82285
摘要： The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped region in the first layer of epitaxial material, forming a second layer of epitaxial material above the first layer of epitaxial material, forming a second doped region in the second layer of epitaxial material, and performing at least one heat treating process.
摘要翻译：本发明一般涉及在集成电路器件中形成p阱的方法。在一个说明性实施例中，该方法包括在衬底的有源层上方形成外延材料的第一层，在第一外延材料层中形成第一掺杂区，在外延材料的第一层之上形成第二层外延材料在所述第二外延材料层中形成第二掺杂区，并进行至少一个热处理工艺。

7. 发明申请

US20060006498A1 Bipolar transistor with geometry optimized for device performance, and method of making same 失效
标题翻译：具有针对器件性能优化的几何形状的双极晶体管及其制造方法
公开(公告)号：US20060006498A1
公开(公告)日：2006-01-12
申请号：US10885250
申请日：2004-07-06
申请人： Ranadeep Dutta
发明人： Ranadeep Dutta
IPC分类号： H01L27/082
CPC分类号： H01L29/73 , H01L29/0692
摘要： The present invention is generally directed to bipolar transistors with geometry optimized for device performance and various methods of making same. In one illustrative embodiment, the device includes a substrate, an intrinsic base region formed in the substrate, a continuous emitter region formed within the intrinsic base region, the emitter region having a plurality of substantially hexagonal shaped openings defined therein, and a plurality of extrinsic base regions formed in the substrate, wherein each of the extrinsic base regions is positioned within an area defined by one of the plurality of substantially hexagonal shaped openings.
摘要翻译：本发明一般涉及具有针对器件性能优化的几何形状的双极晶体管及其制造方法。在一个说明性实施例中，器件包括衬底，形成在衬底中的本征基极区域，形成在本征基极区域内的连续发射极区域，发射极区域具有限定在其中的多个基本上六边形形状的开口，以及多个外部形成在基板中的基部区域，其中每个非本征基极区域位于由多个基本六边形形状的开口之一限定的区域内。

8. 发明授权

US07507608B2 IGBT with amorphous silicon transparent collector 有权
标题翻译： IGBT与非晶硅透明集电极
公开(公告)号：US07507608B2
公开(公告)日：2009-03-24
申请号：US11297571
申请日：2005-12-08
申请人： Richard Francis , Chiu Ng , Hamilton Lu , Ranadeep Dutta
发明人： Richard Francis , Chiu Ng , Hamilton Lu , Ranadeep Dutta
IPC分类号： H01L21/332
CPC分类号： H01L29/66333 , H01L29/0834 , H01L29/7395
摘要： The collector or anode of a non-punch through IGBT formed in a float zone silicon wafer is formed by a P doped amorphous silicon layer deposited on the back surface of an ultra thin wafer. A DMOS structure is formed on the top surface of the wafer before the bottom structure is formed. A back contact is formed over the amorphous silicon layer. No alloy step is needed to activate the anode defined by the P type amorphous silicon.
摘要翻译：形成在浮动区硅晶片中的非穿通IGBT的集电极或阳极由沉积在超薄晶片的背表面上的P掺杂非晶硅层形成。在形成底部结构之前，在晶片的顶表面上形成DMOS结构。在非晶硅层上形成背接触。不需要合金步骤来激活由P型非晶硅限定的阳极。

9. 发明授权

US06627961B1 Hybrid IGBT and MOSFET for zero current at zero voltage 有权
标题翻译：用于零电压零电流的混合IGBT和MOSFET
公开(公告)号：US06627961B1
公开(公告)日：2003-09-30
申请号：US09565151
申请日：2000-05-05
申请人： Richard Francis , Ranadeep Dutta , Chiu Ng , Peter Wood
发明人： Richard Francis , Ranadeep Dutta , Chiu Ng , Peter Wood
IPC分类号： H01L2972
CPC分类号： H01L29/7395
摘要： A high voltage MOSgated semiconductor device has a generally linear MOSFET type forward current versus forward voltage characteristic at low voltage and the high current, low forward drop capability of an IGBT. The device is particularly useful as the control transistor for a television tube deflection coil. The device is formed by a copacked discrete IGBT die and power MOSFET die in which the ratio of the MOSFET die area is preferably about 25% that of the IGBT. Alternatively, the IGBT and MOSFET can be integrated into the same die, with the IGBT and MOSFET elements alternating laterally with one another and overlying respective P+ injection regions and N+ contact regions respectively on the bottom of the die. The MOSFET and IGBT elements are preferably spaced apart by a distance of about 1 minority carrier length (50-100 microns for a 1500 volt device).
摘要翻译：高压MOS电容半导体器件具有大致线性的MOSFET型正向电流与低电压时的正向电压特性以及IGBT的高电流，低正向下降能力。该装置特别适用于电视机管偏转线圈的控制晶体管。该器件由共模封装的分立IGBT管芯和功率MOSFET管芯形成，其中MOSFET管芯面积的比率优选为IGBT的约25％。或者，IGBT和MOSFET可以集成到相同的管芯中，其中IGBT和MOSFET元件彼此横向交替并且分别叠置在管芯底部上的相应的P +注入区域和N +接触区域。 MOSFET和IGBT元件优选地间隔开约1个少数载流子长度（对于1500伏装置为50-100微米）的距离。

10. 发明授权

US06441455B1 Low dosage field rings for high voltage semiconductor device 失效
标题翻译：用于高压半导体器件的低剂量场环
公开(公告)号：US06441455B1
公开(公告)日：2002-08-27
申请号：US08812848
申请日：1997-03-06
申请人： Ranadeep Dutta
发明人： Ranadeep Dutta
IPC分类号： H01L2358
CPC分类号： H01L29/0619 , H01L2924/0002 , H01L2924/00
摘要： The active area of a semiconductor die is surrounded by a plurality of concentrically spaced ring shaped P type diffusions. The diffusions have a low concentration produced by a total boron implant dose of from about 2E12 to 5E13 atoms/cm2. Four to twelve rings are used to terminate an active area at a potential of 600 to 1200 volts with respect to the die street.
摘要翻译：半导体管芯的有源区域由多个同心间隔的环形P型扩散体围绕。扩散具有由约2E12至5E13原子/ cm2的总硼注入剂量产生的低浓度。四到十二个环用于终止相对于模具街道的电压为600至1200伏特的有源区域。

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