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1. 发明授权

US5887183A Method and system in a data processing system for loading and storing vectors in a plurality of modes 失效
标题翻译：用于以多种模式加载和存储向量的数据处理系统中的方法和系统
公开(公告)号：US5887183A
公开(公告)日：1999-03-23
申请号：US368173
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Terry L. Lyon , Brett Olsson , James B. Shearer
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Terry L. Lyon , Brett Olsson , James B. Shearer
IPC分类号： G06F9/312 , G06F15/80
CPC分类号： G06F9/30043 , G06F15/8092 , G06F9/30036
摘要： A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.
摘要翻译：具有多个元素的向量存储在输入存储区域中，其中矢量元素以第一模式存储。此后，元件以第一顺序从输入存储区域传送到向量寄存器接口单元。从矢量寄存器接口单元，将元件传送到输出存储区域，并以多个预选图案之一存储在可寻址位置。输入存储区域可以由高速缓冲存储器或寄存器阵列来实现。输出存储区域可以用高速缓冲存储器或寄存器阵列来实现。输入存储区域中的第一图案可以包括交替的实数和虚部元素。多个预选图案可以包括相反的顺序图案，或者将实数元素和虚构元素分离成两个向量寄存器。

2. 发明授权

US5680338A Method and system for vector processing utilizing selected vector elements 失效
标题翻译：利用选定向量元素进行向量处理的方法和系统
公开(公告)号：US5680338A
公开(公告)日：1997-10-21
申请号：US368172
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson , James B. Shearer
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson , James B. Shearer
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.
摘要翻译：在使用包括多个元素的向量的一部分来处理向量计算的向量处理系统中，提供了用于接收向量和向量处理命令的装置。矢量处理系统还包括用于接收和存储起始元素值和终止元素值的装置。算术逻辑单元耦合到用于接收向量的装置，用于接收向量处理命令的装置和用于接收起始元素和终止元素值的装置。算术逻辑单元还包括仅利用向量中的一个或多个元素来执行向量处理命令的装置，其由起始元素值和终止元素值选择。

3. 发明授权

US5832533A Method and system for addressing registers in a data processing unit in an indexed addressing mode 失效
标题翻译：用于以索引寻址模式寻址数据处理单元中的寄存器的方法和系统
公开(公告)号：US5832533A
公开(公告)日：1998-11-03
申请号：US687825
申请日：1996-07-26
申请人： Ramesh Chandra Agarwal , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
IPC分类号： G06F9/30 , G06F9/318 , G06F9/355 , G06F12/02 , G06F12/06
CPC分类号： G06F9/355 , G06F9/3013 , G06F9/30138
摘要： In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.
摘要翻译：在具有多个通用寄存器的数据处理单元中，加载指令。这样的指令包括操作和至少一个操作数字段，其中操作数字段指定多个基本寄存器中的一个和位移值。为了计算由这样一个操作数字段指定的通用寄存器地址，位移值被添加到存储在由一部分操作数字段指定的基址寄存器中的基础值。最后，数据处理单元利用所计算的通用寄存器地址来寻址所选择的一个通用寄存器，以执行指定的操作。因此，数据处理单元能够寻址比可以使用由操作数字段内的有限数目的位表示的值直接寻址的更大数量的通用寄存器。

4. 发明授权

US5890222A Method and system for addressing registers in a data processing unit in an indirect addressing mode 失效
标题翻译：用于以间接寻址模式寻址数据处理单元中的寄存器的方法和系统
公开(公告)号：US5890222A
公开(公告)日：1999-03-30
申请号：US368176
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , John Joseph Haddow Forrest , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , John Joseph Haddow Forrest , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
IPC分类号： G06F9/30 , G06F9/318 , G06F9/35 , G06F12/00
CPC分类号： G06F9/34 , G06F9/30098 , G06F9/35
摘要： In a data processing unit, an instruction is loaded. Such an instruction includes an operation code field for storing an operation code and at least one operand field, where the operand field includes an indirect addressing mode indicator for indicating enablement of an indirect addressing mode. If an indirect addressing mode is enabled, a general purpose register address is selected from an address field in an indirect register. Finally, the data processing unit addresses a selected one of the plurality of general purpose registers utilizing the general purpose register address during the execution of the operation code by the data processing unit.
摘要翻译：在数据处理单元中，加载指令。这样的指令包括用于存储操作码和至少一个操作数字段的操作码字段，其中操作数字段包括用于指示启用间接寻址模式的间接寻址模式指示符。如果启用间接寻址模式，则从间接寄存器的地址字段中选择通用寄存器地址。最后，在数据处理单元执行操作码期间，数据处理单元利用通用寄存器地址来寻址多个通用寄存器中的选定一个。

5. 发明授权

US5825677A Numerically intensive computer accelerator 失效
标题翻译：数字密集型计算机加速器
公开(公告)号：US5825677A
公开(公告)日：1998-10-20
申请号：US619456
申请日：1996-03-20
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
IPC分类号： G06F17/16 , G06F15/80
CPC分类号： G06F15/8092 , G06F15/8023
摘要： A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.
摘要翻译：描述了允许高速数值计算的矩阵处理单元。处理单元是由多个处理元件形成的矢量处理单元。第I处理单元具有一组N个寄存器，其中存储了N个数据向量的第I个元素或单词。每个处理元件具有能够对N个寄存器组中的N个元素执行算术运算的算术单元。每个数据矢量都有K个元素。因此，有K个处理元素。矩阵处理单元的向量运算同时对两个向量的全部要素进行相同的运算。可以在先前的矢量操作之后的一个机器周期内执行随后的矢量操作。

6. 发明授权

US5758176A Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system 失效
标题翻译：提供用于在超标量数据处理系统内执行单指令多数据操作的单指令多数据执行单元的方法和系统
公开(公告)号：US5758176A
公开(公告)日：1998-05-26
申请号：US313970
申请日：1994-09-28
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
IPC分类号： G06F9/302 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3001 , G06F15/8007 , G06F15/8092 , G06F9/3885 , G06F9/3887
摘要： A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.
摘要翻译：提供了与超标量数据处理系统结合使用的单指令多数据（SIMD）执行单元。 SIMD执行单元耦合到超标量处理器内的分支执行单元。分支执行单元从存储器取出指令，并通过指令总线向SIMD执行单元分派向量处理指令。 SIMD执行单元包括用于执行算术运算的控制单元和多个处理元件。处理元件还包括具有多个寄存器的寄存器文件和耦合到寄存器文件的算术逻辑单元。算术逻辑单元可以包括用于执行定点矢量计算的定点单元和用于执行浮点矢量计算的浮点单元。一旦SIMD执行单元中的控制单元接收到向量指令，则控制单元将该指令转换为SIMD执行单元内的选定处理元件执行的命令。如果这样的向量指令需要访问存储器，则可以利用超标量处理器内的固定点执行单元来计算存储器地址，然后SIMD执行单元利用存储器地址访问存储器。

7. 发明授权

US5513366A Method and system for dynamically reconfiguring a register file in a vector processor 失效
标题翻译：用于在矢量处理器中动态地重新配置寄存器文件的方法和系统
公开(公告)号：US5513366A
公开(公告)日：1996-04-30
申请号：US313971
申请日：1994-09-28
申请人： Ramesh C. Agarwal , Randall D. Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
发明人： Ramesh C. Agarwal , Randall D. Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
IPC分类号： G06F9/30 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F15/8092 , G06F15/8084 , G06F9/30036 , G06F9/30109 , G06F9/30112
摘要： A controller is coupled to a plurality of registers arranged in an array having a physical configuration of N rows of registers and M columns of registers. A size register within the controller is provided for receiving a selected vector size parameter, which specifies a number of registers comprising a vector register. In response to the vector size parameter, columns in the register array are selected and concatenated to form a vector register having at least a number of registers equal to the vector size parameter. An offset parameter may be utilized to select columns that form a vector register from the M number of columns in the array. Multiple arithmetic logic units, where one arithmetic logic unit is coupled to each row of registers are utilized to perform vector operations. Any register in the array may be utilized to store a vector element or a scalar expression. Vector register lengths, and the number of vector registers, may be dynamically configured by setting the vector size parameter and the offset parameter in the controller.
摘要翻译：控制器耦合到排列成具有N行寄存器和M列寄存器的物理配置的阵列中的多个寄存器。提供控制器内的大小寄存器用于接收所选择的向量大小参数，该参数指定包括向量寄存器的寄存器的数量。响应于向量大小参数，选择并连接寄存器阵列中的列并形成具有等于矢量大小参数的至少一些寄存器数量的向量寄存器。偏移参数可用于从阵列中的M列数中选择形成向量寄存器的列。利用多个算术逻辑单元，其中一个算术逻辑单元耦合到每行寄存器用于执行向量操作。阵列中的任何寄存器可用于存储向量元素或标量表达式。矢量寄存器长度和向量寄存器数可以通过在控制器中设置矢量大小参数和偏移参数来动态配置。

8. 发明申请

US20110131394A1 APPARATUS AND METHOD FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS 失效
标题翻译：使用分支预测机制确定跟踪形成准备的装置和方法
公开(公告)号：US20110131394A1
公开(公告)日：2011-06-02
申请号：US13016144
申请日：2011-01-28
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

9. 发明授权

US07877582B2 Multi-addressable register file 失效
标题翻译：多地址寄存器文件
公开(公告)号：US07877582B2
公开(公告)日：2011-01-25
申请号：US12023720
申请日：2008-01-31
申请人： Michael K. Gschwind , Brett Olsson
发明人： Michael K. Gschwind , Brett Olsson
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/3013 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/30145
摘要： A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instructions, SIMD instructions, etc., while the entire set of registers may be addressed with yet another form of instructions, referred to herein as Vector-Scalar Extension (VSX) instructions. The operation set that may be performed on the entire set of registers using the VSX instruction form is substantially similar to that of the operation sets of the subsets of registers. Such an arrangement allows legacy instructions to access subsets of registers within the multi-addressable register file while new instructions, i.e. the VSX instructions, may access the entire range of registers within the multi-addressable register file.
摘要翻译：可以使用标量和SIMD指令来寻址单个寄存器文件。也就是说，根据说明性实施例的多可寻址寄存器堆中的寄存器子集可以用不同的指令形式（例如标量指令，SIMD指令等）寻址，而整个寄存器组可以用另一形式的指令，这里称为矢量 - 标量延伸（VSX）指令。可以使用VSX指令形式在整个寄存器组上执行的操作集基本上类似于寄存器子集的操作集。这种布置允许传统指令访问多址寻址寄存器文件内的寄存器子集，而新的指令即VSX指令可以访问多址寻址寄存器堆中的整个寄存器范围。

10. 发明授权

US07793081B2 Implementing instruction set architectures with non-contiguous register file specifiers 有权
标题翻译：用不连续的寄存器文件说明符来实现指令集体系结构
公开(公告)号：US07793081B2
公开(公告)日：2010-09-07
申请号：US12062131
申请日：2008-04-03
申请人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
发明人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。固定宽度指令包括不连续的寄存器说明符。

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