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1. 发明授权

US5513366A Method and system for dynamically reconfiguring a register file in a vector processor 失效
标题翻译：用于在矢量处理器中动态地重新配置寄存器文件的方法和系统
公开(公告)号：US5513366A
公开(公告)日：1996-04-30
申请号：US313971
申请日：1994-09-28
申请人： Ramesh C. Agarwal , Randall D. Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
发明人： Ramesh C. Agarwal , Randall D. Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
IPC分类号： G06F9/30 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F15/8092 , G06F15/8084 , G06F9/30036 , G06F9/30109 , G06F9/30112
摘要： A controller is coupled to a plurality of registers arranged in an array having a physical configuration of N rows of registers and M columns of registers. A size register within the controller is provided for receiving a selected vector size parameter, which specifies a number of registers comprising a vector register. In response to the vector size parameter, columns in the register array are selected and concatenated to form a vector register having at least a number of registers equal to the vector size parameter. An offset parameter may be utilized to select columns that form a vector register from the M number of columns in the array. Multiple arithmetic logic units, where one arithmetic logic unit is coupled to each row of registers are utilized to perform vector operations. Any register in the array may be utilized to store a vector element or a scalar expression. Vector register lengths, and the number of vector registers, may be dynamically configured by setting the vector size parameter and the offset parameter in the controller.
摘要翻译：控制器耦合到排列成具有N行寄存器和M列寄存器的物理配置的阵列中的多个寄存器。提供控制器内的大小寄存器用于接收所选择的向量大小参数，该参数指定包括向量寄存器的寄存器的数量。响应于向量大小参数，选择并连接寄存器阵列中的列并形成具有等于矢量大小参数的至少一些寄存器数量的向量寄存器。偏移参数可用于从阵列中的M列数中选择形成向量寄存器的列。利用多个算术逻辑单元，其中一个算术逻辑单元耦合到每行寄存器用于执行向量操作。阵列中的任何寄存器可用于存储向量元素或标量表达式。矢量寄存器长度和向量寄存器数可以通过在控制器中设置矢量大小参数和偏移参数来动态配置。

2. 发明授权

US5680338A Method and system for vector processing utilizing selected vector elements 失效
标题翻译：利用选定向量元素进行向量处理的方法和系统
公开(公告)号：US5680338A
公开(公告)日：1997-10-21
申请号：US368172
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson , James B. Shearer
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson , James B. Shearer
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.
摘要翻译：在使用包括多个元素的向量的一部分来处理向量计算的向量处理系统中，提供了用于接收向量和向量处理命令的装置。矢量处理系统还包括用于接收和存储起始元素值和终止元素值的装置。算术逻辑单元耦合到用于接收向量的装置，用于接收向量处理命令的装置和用于接收起始元素和终止元素值的装置。算术逻辑单元还包括仅利用向量中的一个或多个元素来执行向量处理命令的装置，其由起始元素值和终止元素值选择。

3. 发明授权

US06842765B2 Processor design for extended-precision arithmetic 失效
标题翻译：处理器设计用于扩展精度算术
公开(公告)号：US06842765B2
公开(公告)日：2005-01-11
申请号：US09918814
申请日：2001-07-31
申请人： Robert F. Enenkel , Fred G. Gustavson , Bruce M. Fleischer , Jose E. Moreira
发明人： Robert F. Enenkel , Fred G. Gustavson , Bruce M. Fleischer , Jose E. Moreira
IPC分类号： G06F7/38 , G06F7/483 , G06F7/499 , G06F7/544 , G06F19/00
CPC分类号： G06F7/483 , G06F7/49942 , G06F7/5443
摘要： A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the result D is a canonical-form extended-precision floating point number having a high order component and a low order component. The processor is a fused multiply-add processor with a multiplier, an adder, a normalizer and a rounder. The post-adder data path, the normalizer and the rounder each have a data width sufficient to represent post-adder intermediate results to permit the high and low order words of a correctly-rounded result D to be computed. The mantissas of the extended-precision result D are provided such that the high order word mantissa is stored to double precision registers.
摘要翻译：用于对乘法器A，乘法器B和加数C执行乘法加法指令的处理器，以计算结果D.操作数是双精度浮点数，结果D是规范形式的扩展精度具有高阶分量和低阶分量的浮点数。处理器是具有乘法器，加法器，归一化器和舍入器的融合乘法加法器。后加法器数据路径，归一化器和舍入器各自具有足以表示后加法器中间结果的数据宽度，以允许计算正确舍入结果D的高位和低位字。提供扩展精度结果D的尾数，使得高阶字尾被存储到双精度寄存器。

4. 发明授权

US5890222A Method and system for addressing registers in a data processing unit in an indirect addressing mode 失效
标题翻译：用于以间接寻址模式寻址数据处理单元中的寄存器的方法和系统
公开(公告)号：US5890222A
公开(公告)日：1999-03-30
申请号：US368176
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , John Joseph Haddow Forrest , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , John Joseph Haddow Forrest , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
IPC分类号： G06F9/30 , G06F9/318 , G06F9/35 , G06F12/00
CPC分类号： G06F9/34 , G06F9/30098 , G06F9/35
摘要： In a data processing unit, an instruction is loaded. Such an instruction includes an operation code field for storing an operation code and at least one operand field, where the operand field includes an indirect addressing mode indicator for indicating enablement of an indirect addressing mode. If an indirect addressing mode is enabled, a general purpose register address is selected from an address field in an indirect register. Finally, the data processing unit addresses a selected one of the plurality of general purpose registers utilizing the general purpose register address during the execution of the operation code by the data processing unit.
摘要翻译：在数据处理单元中，加载指令。这样的指令包括用于存储操作码和至少一个操作数字段的操作码字段，其中操作数字段包括用于指示启用间接寻址模式的间接寻址模式指示符。如果启用间接寻址模式，则从间接寄存器的地址字段中选择通用寄存器地址。最后，在数据处理单元执行操作码期间，数据处理单元利用通用寄存器地址来寻址多个通用寄存器中的选定一个。

5. 发明授权

US5887183A Method and system in a data processing system for loading and storing vectors in a plurality of modes 失效
标题翻译：用于以多种模式加载和存储向量的数据处理系统中的方法和系统
公开(公告)号：US5887183A
公开(公告)日：1999-03-23
申请号：US368173
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Terry L. Lyon , Brett Olsson , James B. Shearer
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Terry L. Lyon , Brett Olsson , James B. Shearer
IPC分类号： G06F9/312 , G06F15/80
CPC分类号： G06F9/30043 , G06F15/8092 , G06F9/30036
摘要： A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.
摘要翻译：具有多个元素的向量存储在输入存储区域中，其中矢量元素以第一模式存储。此后，元件以第一顺序从输入存储区域传送到向量寄存器接口单元。从矢量寄存器接口单元，将元件传送到输出存储区域，并以多个预选图案之一存储在可寻址位置。输入存储区域可以由高速缓冲存储器或寄存器阵列来实现。输出存储区域可以用高速缓冲存储器或寄存器阵列来实现。输入存储区域中的第一图案可以包括交替的实数和虚部元素。多个预选图案可以包括相反的顺序图案，或者将实数元素和虚构元素分离成两个向量寄存器。

6. 发明授权

US5832533A Method and system for addressing registers in a data processing unit in an indexed addressing mode 失效
标题翻译：用于以索引寻址模式寻址数据处理单元中的寄存器的方法和系统
公开(公告)号：US5832533A
公开(公告)日：1998-11-03
申请号：US687825
申请日：1996-07-26
申请人： Ramesh Chandra Agarwal , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , Fred G. Gustavson , Mark A. Johnson , Brett Olsson
IPC分类号： G06F9/30 , G06F9/318 , G06F9/355 , G06F12/02 , G06F12/06
CPC分类号： G06F9/355 , G06F9/3013 , G06F9/30138
摘要： In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.
摘要翻译：在具有多个通用寄存器的数据处理单元中，加载指令。这样的指令包括操作和至少一个操作数字段，其中操作数字段指定多个基本寄存器中的一个和位移值。为了计算由这样一个操作数字段指定的通用寄存器地址，位移值被添加到存储在由一部分操作数字段指定的基址寄存器中的基础值。最后，数据处理单元利用所计算的通用寄存器地址来寻址所选择的一个通用寄存器，以执行指定的操作。因此，数据处理单元能够寻址比可以使用由操作数字段内的有限数目的位表示的值直接寻址的更大数量的通用寄存器。

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