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1. 发明授权

US08492821B2 Enhanced capacitance trench capacitor 有权
标题翻译：增强电容沟槽电容
公开(公告)号：US08492821B2
公开(公告)日：2013-07-23
申请号：US13434883
申请日：2012-03-30
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：包括沟槽电容器的集成电路具有半导体区域，其中材料组成在其中至少一个分量的量变化，使得该量在至少两个不同值之间多次交替深度。例如，半导体合金中的掺杂剂的浓度或第二半导体材料（例如锗）的重量百分比可以在较高和较低值之间的深度之间交替多次。沟槽电容器具有波动的电容器介电层，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

2. 发明授权

US08227311B2 Method of forming enhanced capacitance trench capacitor 有权
标题翻译：形成增强型电容沟槽电容器的方法
公开(公告)号：US08227311B2
公开(公告)日：2012-07-24
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L21/8242
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

3. 发明申请

US20120086064A1 METHOD OF FORMING ENHANCED CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：形成增强型电容式电容器的方法
公开(公告)号：US20120086064A1
公开(公告)日：2012-04-12
申请号：US12900095
申请日：2010-10-07
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：提供一种制造沟槽电容器的方法，其中衬底的半导体区域的材料组成在其中的至少一个分量的量中变化，使得该量在至少两个不同值之间多次与深度交替。例如，半导体合金中的掺杂剂的浓度或第二半导体材料的重量百分比可以在较高和较低值之间的深度之间交替多次。在这种方法中，可以以取决于材料组成的方式蚀刻半导体区域，以形成具有在与半导体区域的主表面的深度方向上起伏的内表面的沟槽。这种方法还可以包括形成具有波状电容器介电层的沟槽电容器，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

4. 发明申请

US20120187465A1 ENHANCED CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：增强型电容式电容器
公开(公告)号：US20120187465A1
公开(公告)日：2012-07-26
申请号：US13434883
申请日：2012-03-30
申请人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
发明人： Kangguo Cheng , Byeong Y. Kim , Munir D. Naeem , James P. Norum
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/1087 , H01L28/84 , H01L29/66181 , H01L29/945
摘要： An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory (“DRAM”) cell, for example.
摘要翻译：包括沟槽电容器的集成电路具有半导体区域，其中材料组成在其中至少一个分量的量变化，使得该量在至少两个不同值之间多次交替深度。例如，半导体合金中的掺杂剂的浓度或第二半导体材料（例如锗）的重量百分比可以在较高和较低值之间的深度之间交替多次。沟槽电容器具有波动的电容器介电层，其中电容器介电层的起伏至少部分地由沟槽的起伏内表面确定。这种沟槽电容器可以提供增强的电容，并且可以并入诸如动态随机存取存储器（“DRAM”）的存储单元中。

5. 发明授权

US08003488B2 Shallow trench isolation structure compatible with SOI embedded DRAM 有权
标题翻译：浅沟槽隔离结构与SOI嵌入式DRAM兼容
公开(公告)号：US08003488B2
公开(公告)日：2011-08-23
申请号：US11861614
申请日：2007-09-26
申请人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
发明人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译：在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。在深沟槽中形成导电沟槽填充区域。施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

6. 发明申请

US20090079027A1 SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM 有权
标题翻译：与SOI嵌入式DRAM兼容的稳定隔离结构
公开(公告)号：US20090079027A1
公开(公告)日：2009-03-26
申请号：US11861614
申请日：2007-09-26
申请人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
发明人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译：在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。在深沟槽中形成导电沟槽填充区域。施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

7. 发明申请

US20100193852A1 EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION 有权
标题翻译：嵌入式DRAM记忆体与附加图案层，用于改进的形成
公开(公告)号：US20100193852A1
公开(公告)日：2010-08-05
申请号：US12698293
申请日：2010-02-02
申请人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
发明人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
IPC分类号： H01L27/108 , H01L21/8242 , G06F17/50
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。然后蚀刻层状半导体结构。图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

8. 发明授权

US08426268B2 Embedded DRAM memory cell with additional patterning layer for improved strap formation 有权
标题翻译：具有附加图形层的嵌入式DRAM存储单元，用于改善表带形成
公开(公告)号：US08426268B2
公开(公告)日：2013-04-23
申请号：US12698293
申请日：2010-02-02
申请人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
发明人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。然后蚀刻层状半导体结构。图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

9. 发明授权

US07547608B2 Polysilicon hard mask for enhanced alignment signal 失效
标题翻译：多晶硅硬掩模，用于增强对准信号
公开(公告)号：US07547608B2
公开(公告)日：2009-06-16
申请号：US11382540
申请日：2006-05-10
申请人： Kangguo Cheng , Johnathan E. Faltermeier , James P. Norum
发明人： Kangguo Cheng , Johnathan E. Faltermeier , James P. Norum
IPC分类号： H01L21/76 , H01L23/544
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/321 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment feature such that the polysilicon layer reaches a first temperature. The polysilicon layer is then annealed with the substrate to raise the polysilicon layer to a second temperature higher than the first temperature. A photoimageable layer is then deposited over the polysilicon layer, after which an alignment signal including light from the alignment feature is received through the annealed polysilicon layer. Using the alignment signal passing through the annealed polysilicon layer from the alignment feature, an exposure system is aligned with the substrate with improved results.
摘要翻译：提供了一种在衬底上形成多晶硅层并且通过多晶硅层将曝光系统与衬底的对准特征对准的方法。在这种方法中，多晶硅层沉积在具有对准特征的衬底上，使得多晶硅层达到第一温度。然后将多晶硅层与衬底退火以将多晶硅层升高到高于第一温度的第二温度。然后在多晶硅层上沉积可光成像层，之后通过退火的多晶硅层接收包括来自对准特征的光的对准信号。使用通过来自对准特征的退火多晶硅层的对准信号，曝光系统与衬底对准，并具有改进的结果。

10. 发明申请

US20100283093A1 Structure and Method to Form EDRAM on SOI Substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20100283093A1
公开(公告)日：2010-11-11
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

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