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1. 发明授权

US06326260B1 Gate prespacers for high density, high performance DRAMs 失效
标题翻译：用于高密度，高性能DRAM的Gate Prepacers
公开(公告)号：US06326260B1
公开(公告)日：2001-12-04
申请号：US09599703
申请日：2000-06-22
申请人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
发明人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823462 , H01L27/10873
摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.
摘要翻译：提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及所述多晶硅层在所述导体材料层上形成氮化物覆盖层形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

2. 发明授权

US08647913B2 Image sensor, method and design structure including non-planar reflector 失效
标题翻译：图像传感器，方法和设计结构包括非平面反射器
公开(公告)号：US08647913B2
公开(公告)日：2014-02-11
申请号：US13614210
申请日：2012-09-13
申请人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
发明人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
IPC分类号： H01L27/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14625 , H01L27/1464 , H01L27/14683 , H01L27/14685
摘要： A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.
摘要翻译：固态图像传感器，制造固态图像传感器的方法和用于制造固态图像传感器结构的设计结构包括依次包括感光区域的基板。还包括在固态图像传感器内的非平面反射器层位于感光区域和基板的与感光区域和基板的入射辐射侧相对的一侧上。非平面反射器层被成形和定位成将未捕获的入射辐射反射回光敏区域，同时避免与衬底内横向分离的附加光敏区域的光学串扰。

3. 发明授权

US07790559B2 Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes 失效
标题翻译：具有高K栅极电介质层和金属栅电极的半导体晶体管
公开(公告)号：US07790559B2
公开(公告)日：2010-09-07
申请号：US12038195
申请日：2008-02-27
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构及其形成方法。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

4. 发明授权

US08227874B2 Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes 有权
标题翻译：具有高K栅极电介质层和金属栅电极的半导体晶体管
公开(公告)号：US08227874B2
公开(公告)日：2012-07-24
申请号：US12861913
申请日：2010-08-24
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

5. 发明申请

US20090212376A1 SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS AND METAL GATE ELECTRODES 失效
标题翻译：具有高K栅电介质层和金属栅极电极的半导体晶体管
公开(公告)号：US20090212376A1
公开(公告)日：2009-08-27
申请号：US12038195
申请日：2008-02-27
申请人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
发明人： James William Adkisson , Michael Patrick Chudzik , Jeffrey Peter Gambino , Hongwen Yan
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/1037 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.
摘要翻译：半导体结构及其形成方法。半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和（v）第一栅介质角区域。最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii））不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

6. 发明授权

US07492048B2 CMOS sensors having charge pushing regions 失效
标题翻译： CMOS传感器具有电荷推送区域
公开(公告)号：US07492048B2
公开(公告)日：2009-02-17
申请号：US11275497
申请日：2006-01-10
申请人： James William Adkisson , Jeffrey Peter Gambino , Mark David Jaffe , Jeffrey Bowman Johnson , Jerome Brett Lasky , Richard John Rassel
发明人： James William Adkisson , Jeffrey Peter Gambino , Mark David Jaffe , Jeffrey Bowman Johnson , Jerome Brett Lasky , Richard John Rassel
IPC分类号： H01L31/062
CPC分类号： H01L27/1462 , H01L27/14603 , H01L27/1463
摘要： Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.
摘要翻译：结构及其形成方法。该半导体结构包括包含第一半导体区域和第二半导体区域的光电二极管。第一和第二半导体区域分别掺杂有第一和第二掺杂极性，并且第一和第二掺杂极性相反。半导体结构还包括传输门，其包括（i）第一延伸区，（ii）第二延伸区和（iii）浮动扩散区。第一和第二延伸区分别与光电二极管和浮动扩散区直接物理接触。半导体结构还包括电荷推送区域。电荷推送区域与第一半导体区域重叠，并且不与浮动扩散区域重叠。电荷推送区域包括透明且导电的材料。

7. 发明申请

US20130001727A1 IMAGE SENSOR, METHOD AND DESIGN STRUCTURE INCLUDING NON-PLANAR REFLECTOR 失效
标题翻译：图像传感器，包括非平面反射器的方法和设计结构
公开(公告)号：US20130001727A1
公开(公告)日：2013-01-03
申请号：US13614210
申请日：2012-09-13
申请人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
发明人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14625 , H01L27/1464 , H01L27/14683 , H01L27/14685
摘要： A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.
摘要翻译：固态图像传感器，制造固态图像传感器的方法和用于制造固态图像传感器结构的设计结构包括依次包括感光区域的基板。还包括在固态图像传感器内的非平面反射器层位于感光区域和基板的与感光区域和基板的入射辐射侧相对的一侧上。非平面反射器层被成形和定位成将未捕获的入射辐射反射回光敏区域，同时避免与衬底内横向分离的附加光敏区域的光学串扰。

8. 发明授权

US08232612B2 Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances 有权
标题翻译：具有高K栅极电介质层，金属栅电极区域和低边缘电容的半导体晶体管
公开(公告)号：US08232612B2
公开(公告)日：2012-07-31
申请号：US12645981
申请日：2009-12-23
申请人： James William Adkisson , Michael P. Chudzik , Jeffrey Peter Gambino , Renee T. Mo , Naim Moumen
发明人： James William Adkisson , Michael P. Chudzik , Jeffrey Peter Gambino , Renee T. Mo , Naim Moumen
IPC分类号： H01L21/00
CPC分类号： H01L29/4983 , H01L29/4966 , H01L29/518 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A semiconductor structure. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.
摘要翻译：半导体结构。该结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）栅极电介质区，和（iv）栅电极区，（v）栅电极区上的多个互连层，以及（vi）第一和第二空间。栅极电介质区域设置在沟道区域和栅电极区域之间并与其直接物理接触。栅电极区域设置在栅极电介质区域和互连层之间并与其直接物理接触。第一和第二空间与栅电极区域直接物理接触。第一空间设置在第一源极/漏极区域和栅极电极区域之间。第二空间设置在第二源极/漏极区域和栅极电极区域之间。

9. 发明申请

US20110049330A1 IMAGE SENSOR, METHOD AND DESIGN STRUCTURE INCLUDING NON-PLANAR REFLECTOR 有权
标题翻译：图像传感器，包括非平面反射器的方法和设计结构
公开(公告)号：US20110049330A1
公开(公告)日：2011-03-03
申请号：US12550640
申请日：2009-08-31
申请人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
发明人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
IPC分类号： H01L27/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14625 , H01L27/1464 , H01L27/14683 , H01L27/14685
摘要： A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.
摘要翻译：固态图像传感器，制造固态图像传感器的方法和用于制造固态图像传感器结构的设计结构包括依次包括感光区域的基板。还包括在固态图像传感器内的非平面反射器层位于感光区域和基板的与感光区域和基板的入射辐射侧相对的一侧上。非平面反射器层被成形和定位成将未捕获的入射辐射反射回光敏区域，同时避免与衬底内横向分离的附加光敏区域的光学串扰。

10. 发明授权

US07687340B2 Protect diodes for hybrid-orientation substrate structures 失效
标题翻译：用于混合取向衬底结构的保护二极管
公开(公告)号：US07687340B2
公开(公告)日：2010-03-30
申请号：US11849489
申请日：2007-09-04
申请人： James William Adkisson , Jeffrey Peter Gambino , Alain Loiseau , Kirk David Peterson
发明人： James William Adkisson , Jeffrey Peter Gambino , Alain Loiseau , Kirk David Peterson
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.
摘要翻译：半导体结构制造方法。首先，提供半导体结构，其包括：（a）具有掺杂有第一掺杂极性且具有第一晶格取向的第一半导体材料的半导体块，以及（b）半导体块上的半导体区域，其中半导体区域是物理上的并且其中所述半导体区域包括掺杂有与所述第一掺杂极性相反的第二掺杂极性的第二半导体材料（i）和（ii）具有不同于所述第一晶格取向的第二晶格取向。接下来，分别在半导体块和半导体区域上形成第一和第二栅极叠层。然后，（i）第一和第二S / D区域同时形成在半导体块中的第一栅极堆叠的相对侧上，以及（ii）半导体块中的第一和第二放电预防半导体区域。

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