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1. 发明授权

US4713631A Varactor tuning circuit having plural selectable bias voltages 失效
标题翻译：变容二极管调谐电路具有多个可选偏置电压
公开(公告)号：US4713631A
公开(公告)日：1987-12-15
申请号：US816589
申请日：1986-01-06
申请人： Ralph T. Enderby , Enrique Ferrer , Wayne P. Shepherd
发明人： Ralph T. Enderby , Enrique Ferrer , Wayne P. Shepherd
IPC分类号： H03H5/12 , H03B1/00 , H03J5/02 , H03J5/24 , H03L7/099 , H03L7/187 , H04B1/40 , H03B5/08 , H03L7/18
CPC分类号： H03L7/187 , H03L7/099 , H03B2201/0208 , H03L2207/06
摘要： A variable capacitance circuit includes a varactor having an anode side and a cathode side. A first variable bias voltage is applied to one of the sides and one of a plurality of voltages is applied as a second bias voltage to the other side for controlling the capacitance of the varactor. A voltage multiplier circuit connected to a voltage divider network is used for supplying the plurality of voltages. A decoder is responsive to input signals for selecting and applying one of the multiple voltage outputs. The variable capacitance circuit is used in a voltage controlled oscillator of a frequency synthesizer for providing extended frequency range.
摘要翻译：可变电容电路包括具有阳极侧和阴极侧的变容二极管。将一个可变偏置电压施加到一个侧面，并且将多个电压中的一个作为第二偏置电压施加到另一侧以控制变容二极管的电容。连接到分压网络的电压倍增器电路用于提供多个电压。解码器响应于用于选择和施加多个电压输出中的一个的输入信号。可变电容电路用于频率合成器的压控振荡器，用于提供扩展的频率范围。

2. 发明授权

US5021754A Fractional-N synthesizer having modulation spur compensation 失效
标题翻译：具有调制支路补偿的分数N合成器
公开(公告)号：US5021754A
公开(公告)日：1991-06-04
申请号：US553472
申请日：1990-07-16
申请人： Wayne P. Shepherd , Darrell E. Davis , Wan F. Tay
发明人： Wayne P. Shepherd , Darrell E. Davis , Wan F. Tay
IPC分类号： H03C3/00 , H03C3/09 , H03L7/183 , H03L7/197
CPC分类号： H03C3/0933 , H03C3/0925 , H03L7/1976
摘要： A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.
摘要翻译：具有杂散补偿的合成器电路利用合成器回路中的分数除法。分数分频器包括当分数分子N = 0时补偿杂散的装置。合成器包括用于选择参考因数R以使得产生分数分子的非零值并且使得所产生的杂散低于合成器的压控振荡器的边带噪声极限的装置。

3. 发明授权

US4994768A Frequency synthesizer with FM modulation 失效
标题翻译：带FM调制的频率合成器
公开(公告)号：US4994768A
公开(公告)日：1991-02-19
申请号：US499102
申请日：1990-03-26
申请人： Wayne P. Shepherd , Darrell E. Davis , Frederick L. Martin
发明人： Wayne P. Shepherd , Darrell E. Davis , Frederick L. Martin
IPC分类号： H03C3/09
CPC分类号： H03C3/0966 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0958
摘要： A frequency synthesizer (10) for providing a modulated output signal (fo) includes a reference frequency signal (fr) and a voltage controlled oscillator (14). For dividing the frequency of the output signal from the voltage controlled oscillator (14) by a divisor, a programmable divider (16) is coupled to the output of the voltage controlled oscillator (14). To produce a phase-locked loop in which the frequency of the output signal from the voltage controlled oscillator (14) is equal to the frequency of the reference frequency (fr) signal multiplied by the divisor, a phase detector (12 ) having a first input coupled to the reference frequency signal (fr), a second input coupled to the output of the programmable divider (16), and an output coupled to the input of the voltage controlled oscillator (14) is also provided. A first integrator (24) for integrating a modulating signal provides an integrated signal and a first control signal. Similarly, a second integrator (25) coupled to the first integrator (24) for integrating the integrated signal provides a second control signal. A differentiator ( 36, 42 and 48) coupled to the second integrator (25) differentiates the second control signal to provide a third control signal. Finally, a processor (41 and 43) coupled to the first integrator (24), the second integrator (25) and the differentiator (36, 42 and 48) processes the first, second, and third control signals and a divider modulus code (M). The processor (41 and 43) coupled to the programmable divider modifies the divider modulus code (M) in response to the modulating signal (9) to provide the divisor, whereby the frequency of the output signal from the voltage controlled oscillator (14) is modulated by the modulating signal (9).
摘要翻译：用于提供调制输出信号（fo）的频率合成器（10）包括参考频率信号（fr）和压控振荡器（14）。为了将来自压控振荡器（14）的输出信号的频率除以除数，可编程分频器（16）耦合到压控振荡器（14）的输出。为了产生锁相环，其中来自压控振荡器（14）的输出信号的频率等于参考频率（fr）信号乘以除数的频率，相位检测器（12）具有第一耦合到参考频率信号（fr）的输入，耦合到可编程分频器（16）的输出的第二输入，以及耦合到压控振荡器（14）的输入的输出。用于对调制信号进行积分的第一积分器（24）提供积分信号和第一控制信号。类似地，耦合到第一积分器（24）的用于积分积分信号的第二积分器（25）提供第二控制信号。耦合到第二积分器（25）的微分器（36,42和48）区分第二控制信号以提供第三控制信号。最后，耦合到第一积分器（24），第二积分器（25）和微分器（36,42和48）的处理器（41和43）处理第一，第二和第三控制信号以及分频器模数 M）。耦合到可编程分配器的处理器（41和43）响应于调制信号（9）来修改分频器模数码（M）以提供除数，由此来自压控振荡器（14）的输出信号的频率为由调制信号（9）调制。

4. 发明授权

US5140196A Variable level translator 失效
标题翻译：可变级别翻译器
公开(公告)号：US5140196A
公开(公告)日：1992-08-18
申请号：US684754
申请日：1991-04-15
申请人： Wayne P. Shepherd
发明人： Wayne P. Shepherd
IPC分类号： H03K19/0175
CPC分类号： H03K19/017581
摘要： A voltage level shifting circuit (100) comprises an input port (160) and output terminal (162). The voltage level shifting circuit (100) further comprises a voltage translation circuit which generates first and second voltage levels, both of which are related to the input reference voltage and which both vary with variations in the input voltage. A control circuit (158) controls which of the two voltage levels produced by the voltage translation circuit is presented at output terminal (162), depending on the voltage level at the control circuit input port (168).
摘要翻译：电压电平移位电路（100）包括输入端口（160）和输出端子（162）。电压电平移位电路（100）还包括产生第一和第二电压电平的电压转换电路，两者电压电平都与输入参考电压相关，并且两者都随着输入电压的变化而变化。根据控制电路输入端口（168）的电压电平，控制电路（158）控制由电压转换电路产生的两个电压电平中的哪一个呈现在输出端（162）。

5. 发明授权

US5331293A Compensated digital frequency synthesizer 失效
标题翻译：补偿数字频率合成器
公开(公告)号：US5331293A
公开(公告)日：1994-07-19
申请号：US940259
申请日：1992-09-02
申请人： Wayne P. Shepherd , Joseph P. Heck
发明人： Wayne P. Shepherd , Joseph P. Heck
IPC分类号： G06F1/03 , H03B1/04 , H03B28/00 , H03C1/04 , H03C3/09 , H03L7/02 , H03L7/16 , H03L7/00 , H04B1/40
CPC分类号： H03C3/09 , G06F1/0328 , H03L7/02 , H03L7/16 , H03B2202/076 , H03B28/00 , H03C1/04
摘要： A digital frequency synthesizer circuit with spur compensation includes a demodulator circuit (118) for demodulating the output signal (116) of the synthesizer's accumulator (108). Demodulator (118) also inverts the signal, and provides an inverted demodulated output signal (142) which is then coupled to the synthesizer clock (124) after passing through a gain stage (122) in order to modulate the synthesizer clock (124) with a compensation signal (146). The compensated clock signal (140) is then sent to accumulator (108) in order to substantially cancel out any jitter in the accumulator's output signal (116). The modulation signal (MOD IN) which is digitally applied to accumulator (108) is applied in analog fashion to the gain stage (122) in order to prevent the desired modulation signal (MOD IN) from being canceled in the output signal (116).
摘要翻译：具有杂散补偿的数字频率合成器电路包括用于解调合成器的累加器（108）的输出信号（116）的解调器电路（118）。解调器（118）还使信号反相，并且提供反向解调的输出信号（142），然后在通过增益级（122）之后耦合到合成器时钟（124），以便用合成器时钟（124）补偿信号（146）。补偿的时钟信号（140）然后被发送到累加器（108），以便基本上消除累加器的输出信号（116）中的任何抖动。数字地施加到累加器（108）的调制信号（MOD IN）以模拟方式施加到增益级（122），以便防止在输出信号（116）中消除所需调制信号（MOD IN）。

6. 发明授权

US4980653A Phase locked loop 失效
标题翻译：锁相环
公开(公告)号：US4980653A
公开(公告)日：1990-12-25
申请号：US402715
申请日：1989-09-05
申请人： Wayne P. Shepherd
发明人： Wayne P. Shepherd
IPC分类号： H03L7/107 , H03L7/18
CPC分类号： H03L7/18 , H03L7/107
摘要： A phase locked loop (100) with a sample and hold phase detector (106) with adjustable gain. A switching circuit adjusts the slew rate of the phase detector by either introducing additional ramp capacitance (122) in the phase detector or by increasing the current for charging the ramp capacitor (116).
摘要翻译：具有可调节增益的采样和保持相位检测器（106）的锁相环（100）。切换电路通过在相位检测器中引入额外的斜坡电容（122）或增加用于对斜坡电容器（116）充电的电流来调节相位检测器的转换速率。

7. 发明授权

US4952889A Loop filter modulated synthesizer 失效
标题翻译：环路滤波器调制合成器
公开(公告)号：US4952889A
公开(公告)日：1990-08-28
申请号：US344640
申请日：1989-04-28
申请人： James S. Irwin , Wayne P. Shepherd
发明人： James S. Irwin , Wayne P. Shepherd
IPC分类号： H03C3/09 , H03L7/089
CPC分类号： H03C3/0975 , H03C3/0941 , H03L7/0891
摘要： A frequency synthesizer for providing a modulated output signal includes a phase comparator, a loop filter, and a voltage controlled oscillator (VCO). The phase comparator receives a reference input signal and a signal related to the VCO output, and generates a control current. A modulation circuit receives a modulation signal and provides both a modulation current and a modulation voltage. The modulation current is summed with the control current at one input of the loop filter, while the modulation voltage is applied to a second input of the loop filter. The VCO is controlled by the output of the loop filter to produce the modulated output signal.
摘要翻译：用于提供调制输出信号的频率合成器包括相位比较器，环路滤波器和压控振荡器（VCO）。相位比较器接收参考输入信号和与VCO输出相关的信号，并产生一个控制电流。调制电路接收调制信号并提供调制电流和调制电压。调制电流与环路滤波器的一个输入处的控制电流相加，而调制电压被施加到环路滤波器的第二输入端。 VCO由环路滤波器的输出控制，以产生调制的输出信号。

8. 发明授权

US4559505A Frequency synthesizer with improved priority channel switching 失效
标题翻译：频率合成器具有改进的优先级信道切换
公开(公告)号：US4559505A
公开(公告)日：1985-12-17
申请号：US455454
申请日：1983-01-04
申请人： Jose I. Suarez , James S. Irwin , Wayne P. Shepherd
发明人： Jose I. Suarez , James S. Irwin , Wayne P. Shepherd
IPC分类号： H03L7/093 , H03L7/10 , H03L7/18 , H03L7/00
CPC分类号： H03L7/093 , H03L7/10 , H03L7/18
摘要： A frequency synthesizer is provided including a reference frequency generator coupled to one input of a phase detector. The output of the phase detector is coupled via a pair of alternatingly connected filters through a voltage controlled oscillator and a divider circuit to the remaining input of the phase detector to form a phase locked loop. The first filter of the pair is designated for operation on a main channel frequency while the remaining filter is designated for operation on a priority channel frequency. The capacitive elements of each respective filter remain fully charged up for operation on their respective frequencies and thus when such filters are alternately switched between to change frequency from the main channel to the priority channel, the capacitive elements need not be charged to new levels to accommodate such frequency change. Thus, switching between a main channel and a priority channel is accomplished in a minimal amount of time with a significant reduction in frequency synthesizer energy requirements.
摘要翻译：提供了包括耦合到相位检测器的一个输入端的参考频率发生器的频率合成器。相位检测器的输出通过一对交替连接的滤波器通过压控振荡器和分频器电路耦合到相位检测器的剩余输入端以形成锁相环。该对的第一个滤波器被指定为在主信道频率上操作，而剩余的滤波器被指定用于在优先信道频率上操作。每个相应滤波器的电容元件保持完全充电以在它们各自的频率上操作，并且因此当这样的滤波器在从主通道到优先通道的频率之间交替切换时，电容元件不需要充电到新的电平以适应这种频率变化。因此，在主要信道和优先信道之间的切换是在最小的时间内实现的，同时频率合成器的能量需求显着降低。

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