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1. 发明授权

US07064074B2 Technique for forming contacts for buried doped regions in a semiconductor device 有权
标题翻译：在半导体器件中形成掩埋掺杂区的接触的技术
公开(公告)号：US07064074B2
公开(公告)日：2006-06-20
申请号：US10624712
申请日：2003-07-22
申请人： Ralf van Bentum , Manfred Horstmann
发明人： Ralf van Bentum , Manfred Horstmann
IPC分类号： H01L21/302
CPC分类号： H01L21/76229 , H01L21/74
摘要： A semiconductor device comprises an isolation trench and a contact trench that may contact a buried conductive region. The contact trench comprises insulating sidewall spacers that are formed during the filling of the isolation trench with an insulating material and the subsequent anisotropic etching of the excess material. Thereafter, the contact trench is filled with a conductive material. Thus, the formation of a contact for a buried region may be carried out simultaneously with the formation of a trench isolation structure, thereby minimizing the number of process steps required.
摘要翻译：半导体器件包括隔离沟槽和可接触埋入导电区域的接触沟槽。接触沟槽包括绝缘侧壁间隔物，其在用隔离材料填充隔离沟槽期间形成，并且随后对多余材料进行各向异性蚀刻。此后，用导电材料填充接触沟槽。因此，可以与形成沟槽隔离结构同时进行掩埋区域的接触的形成，从而最小化所需的工艺步骤的数量。

2. 发明授权

US08440516B2 Method of forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US08440516B2
公开(公告)日：2013-05-14
申请号：US12752487
申请日：2010-04-01
申请人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann
发明人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann
IPC分类号： H01L21/8234
CPC分类号： H01L29/66621 , H01L29/165 , H01L29/66583 , H01L29/7834 , H01L29/7848
摘要： A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.
摘要翻译：形成场效应晶体管的方法包括提供包括半导体材料的双轴应变层的衬底。在半导体材料的双轴应变层上形成栅电极。在栅电极附近形成凸起的源区和升高的漏极区。将掺杂剂材料的离子注入到凸起的源极区域和隆起的漏极区域中，以形成扩展的源极区域和延伸的漏极区域。此外，在形成根据本发明的实施例的场效应晶体管的方法中，可以在半导体材料层的凹部中形成栅电极。因此，可以获得其中位于沟道区附近的源极侧沟道接触区域和漏极侧沟道接触区域受到双轴应变的场效应晶体管。

3. 发明申请

US20120161240A1 Transistor Comprising an Embedded Sigma-Shaped Semiconductor Alloy Having Superior Uniformity 审中-公开
标题翻译：晶体管包括具有优异均匀性的嵌入式Sigma形半导体合金
公开(公告)号：US20120161240A1
公开(公告)日：2012-06-28
申请号：US13337690
申请日：2011-12-27
申请人： Stephan Kronholz , Juergen Amon , Manfred Horstmann
发明人： Stephan Kronholz , Juergen Amon , Manfred Horstmann
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , Y02P80/30
摘要： When incorporating a strain-inducing semiconductor alloy in one type of sophisticated transistors, the removal of sacrificial cap materials, such as a spacer layer, sacrificial spacer elements and dielectric cap materials, may be accomplished by using, at least in a first phase of the removal process, an efficient etch stop liner material, which may thus reduce the material loss in the drain and source extension regions that are formed prior to the deposition of the strain-inducing semiconductor material. Moreover, the drain and source extension regions of the other type of transistor may be formed with superior process uniformity due to a reduced material erosion of the corresponding spacer elements.
摘要翻译：当在一种类型的复杂晶体管中引入应变诱导半导体合金时，可以通过使用至少在第一阶段中的至少第一阶段来完成除去牺牲帽材料，例如间隔层，牺牲隔离元件和电介质盖材料去除工艺，有效的蚀刻停止衬垫材料，其可以因此减少在应变诱导半导体材料的沉积之前形成的漏极和源极延伸区域中的材料损耗。此外，由于相应的间隔元件的材料侵蚀减少，另一种类型的晶体管的漏极和源极延伸区域可以形成为具有优异的工艺均匀性。

4. 发明申请

US20110104878A1 SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 有权
标题翻译：包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件
公开(公告)号：US20110104878A1
公开(公告)日：2011-05-05
申请号：US13005676
申请日：2011-01-13
申请人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
发明人： Sven Beyer , Manfred Horstmann , Patrick Press , Wolfgang Buchholtz
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L29/165 , H01L29/66621 , H01L29/66651 , H01L29/7833 , H01L29/7848 , H01L29/7849
摘要： By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
摘要翻译：通过在一个有源区中形成基本上连续且均匀的半导体合金，同时在第二有源区中图案化半导体合金，以便在其中心部分提供基极半导体材料，可以诱发不同类型的应变，可以使用基底半导体材料的相应的覆盖层，用于形成栅极电介质的完善的工艺技术。在一些示例性实施例中，提供了基本上自对准的工艺，其中栅电极可以基于层形成，其也已经用于限定一个有源区的基极半导体材料的中心部分。因此，通过使用单个半导体合金，可以单独提高不同导电类型的晶体管的性能。

5. 发明授权

US07906383B2 Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device 有权
标题翻译：通过在半导体器件中的应力 - 中性电介质材料上方提供应力介电层，在层间电介质中进行应力转移
公开(公告)号：US07906383B2
公开(公告)日：2011-03-15
申请号：US12045095
申请日：2008-03-10
申请人： Ralf Richter , Andy Wei , Manfred Horstmann , Joerg Hohage
发明人： Ralf Richter , Andy Wei , Manfred Horstmann , Joerg Hohage
IPC分类号： H01L21/8238 , H01L21/311 , H01L21/70 , H01L27/085
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823425 , H01L29/7843
摘要： By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.
摘要翻译：通过在不同的晶体管上形成应力介电层并随后放松其一部分，可以增强用于通过应力覆盖层在晶体管的沟道区域中产生应变的方法中的整体工艺效率，同时可以为每种类型的晶体管获得晶体管性能增益由于位于先前松弛部分之上的高应力材料也可有效地影响底层晶体管。

6. 发明授权

US07696052B2 Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions 有权
标题翻译：通过使漏极和源极区域凹陷来在靠近沟道区域的晶体管中提供应力源的技术
公开(公告)号：US07696052B2
公开(公告)日：2010-04-13
申请号：US11558006
申请日：2006-11-09
申请人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann , Peter Javorka , Joe Bloomquist
发明人： Andy Wei , Thorsten Kammler , Jan Hoentschel , Manfred Horstmann , Peter Javorka , Joe Bloomquist
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/7843 , H01L29/7848 , H01L29/78621 , H01L29/78684
摘要： By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.
摘要翻译：通过凹陷漏极和源极区域，可以在凹部中形成诸如接触蚀刻停止层的高应力层，以增强场效应晶体管的相邻沟道区域中的应变产生。此外，应变半导体材料可以通过减少或避免金属硅化物的不适当的松弛效应来定位在靠近沟道区域，从而也为应变产生提供增强的效率。在一些方面，两种效应可以组合以获得更有效的应变诱导机制。

7. 发明授权

US07659170B2 Method of increasing transistor drive current by recessing an isolation trench 有权
标题翻译：通过凹陷隔离沟槽来增加晶体管驱动电流的方法
公开(公告)号：US07659170B2
公开(公告)日：2010-02-09
申请号：US11620406
申请日：2007-01-05
申请人： Christoph Schwan , Manfred Horstmann , Martin Gerhardt , Markus Forseberg
发明人： Christoph Schwan , Manfred Horstmann , Martin Gerhardt , Markus Forseberg
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L29/665
摘要： By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the formation of the gate electrode, an increased degree of poly wrap around may be obtained, thereby increasing the effective channel width.
摘要翻译：通过在硅化之前使晶体管的隔离结构凹陷，由于在隔离结构附近形成的金属硅化物的量增加，串联电阻可能会降低。通过在形成栅电极之前使隔离结构凹陷，可以获得增加的聚环绕的程度，从而增加有效沟道宽度。

8. 发明授权

US07563731B2 Field effect transistor having a stressed dielectric layer based on an enhanced device topography 有权
标题翻译：基于增强器件形貌的具有应力介电层的场效应晶体管
公开(公告)号：US07563731B2
公开(公告)日：2009-07-21
申请号：US11739279
申请日：2007-04-24
申请人： Christoph Schwan , Manfred Horstmann , Kai Frohberg , Rolf Stephan
发明人： Christoph Schwan , Manfred Horstmann , Kai Frohberg , Rolf Stephan
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , Y10S438/902
摘要： By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.
摘要翻译：通过在形成第一层高应力电介质材料之后增加晶体管形貌，可以添加额外的应力材料，从而有效地增加应力介电材料的整个层厚度。可以基于相应的占位符结构或伪栅极来实现器件形貌的相应增加，其中可以使用完全确定的栅极图案化工艺，或者可以采用纳米压印技术。因此，在一些说明性实施例中，可以基于公认的工艺技术获得应变的显着增加。

9. 发明授权

US07381624B2 Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate 失效
标题翻译：用于形成具有位于结晶体基板上方的具有不同特性的晶体半导体区域的衬底的技术
公开(公告)号：US07381624B2
公开(公告)日：2008-06-03
申请号：US11177214
申请日：2005-07-08
申请人： Andy Wei , Thorsten Kammler , Michael Raab , Manfred Horstmann
发明人： Andy Wei , Thorsten Kammler , Michael Raab , Manfred Horstmann
IPC分类号： H01L21/20
CPC分类号： H01L29/7833 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76254 , H01L21/823807 , H01L29/045 , H01L29/6659
摘要： By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.
摘要翻译：通过直接键合具有不同晶体取向和/或材料组成和/或内部应变的两个晶体半导体层，可以形成块状混合衬底，从而提供根据混合物上的单晶体管结构形成半导体器件的潜力基质。

10. 发明申请

US20080081486A1 FIELD EFFECT TRANSISTOR HAVING A STRESSED DIELECTRIC LAYER BASED ON AN ENHANCED DEVICE TOPOGRAPHY 有权
标题翻译：基于增强型设备地形的具有应力介电层的场效应晶体管
公开(公告)号：US20080081486A1
公开(公告)日：2008-04-03
申请号：US11739279
申请日：2007-04-24
申请人： Christoph Schwan , Manfred Horstmann , Kai Frohberg , Rolf Stephan
发明人： Christoph Schwan , Manfred Horstmann , Kai Frohberg , Rolf Stephan
IPC分类号： H01L21/31
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , Y10S438/902
摘要： By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.
摘要翻译：通过在形成第一层高应力电介质材料之后增加晶体管的形貌，可添加额外的应力材料，从而有效地增加应力介电材料的整个层厚度。可以基于相应的占位符结构或伪栅极来实现器件形貌的相应增加，其中可以使用完全确定的栅极图案化工艺，或者可以采用纳米压印技术。因此，在一些说明性实施例中，可以基于公认的工艺技术获得应变的显着增加。

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