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1. 发明授权

US06943088B2 Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding 失效
标题翻译：制造具有不同角度圆角的半导体器件的沟槽隔离结构的方法
公开(公告)号：US06943088B2
公开(公告)日：2005-09-13
申请号：US10444191
申请日：2003-05-23
申请人： Ralf van Bentum , Stephan Kruegel , Gert Burbach
发明人： Ralf van Bentum , Stephan Kruegel , Gert Burbach
IPC分类号： H01L21/762 , H01L21/331
CPC分类号： H01L21/76235 , H01L21/76229
摘要： In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.
摘要翻译：在半导体器件的沟槽隔离结构中，在沟槽内形成氧化物衬垫，其中在各种氧化步骤期间使用不可氧化的掩模，从而产生不同类型的衬里氧化物，从而产生不同类型的圆角圆角并因此产生机械应力。因此，对于指定类型的电路元件，可以调整相应的隔离沟槽的特性以实现最佳的器件性能。

2. 发明授权

US06787852B1 Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions 有权
标题翻译：具有源极/漏极硅 - 锗区域的绝缘体上半导体（SOI）器件
公开(公告)号：US06787852B1
公开(公告)日：2004-09-07
申请号：US10278420
申请日：2002-10-23
申请人： Bin Yu , Ralf van Bentum
发明人： Bin Yu , Ralf van Bentum
IPC分类号： H01L2701
CPC分类号： H01L29/66477 , H01L21/26506 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78684
摘要： A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer. The active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween. The source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon. The silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.
摘要翻译：绝缘体上半导体（SOI）器件。 SOI器件包括其上设置有掩埋氧化物层的衬底和设置在掩埋氧化物层上的有源层。有源层具有由隔离区域限定的有源区域，有源区域具有源极和漏极，其间设置有主体。源极和漏极具有选择性地生长的硅 - 锗区域，其设置在选择性生长的硅的上层下方。硅锗天线分别沿着源极/主体结和漏极/主体结形成异质结部分。

3. 发明授权

US06774436B1 SOI MOSFET with asymmetrical source/body and drain/body junctions 有权
标题翻译：具有不对称源/体和漏/体结的SOI MOSFET
公开(公告)号：US06774436B1
公开(公告)日：2004-08-10
申请号：US09900400
申请日：2001-07-05
申请人： Bin Yu , Ralf van Bentum
发明人： Bin Yu , Ralf van Bentum
IPC分类号： H01L310392
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78624
摘要： A semiconductor-on-insulator (SOI) device. The SOi device includes a substrate, an insulator layer disposed on the substrate and an active region disposed on the insulator layer. The active region includes a source, a drain, and a body disposed therebetween. The source and body form an abrupt or hyperabrupt source/body junction. A gate is disposed on the body to operatively form a transistor. An implanted region forms an interface between the body and the drain, the implanted region formed by tilted atom implantation in a direction towards the active region and under the gate from an angle tilted towards the drain with respect to vertical, the implanted region resulting in the formation of a graded drain/body junction. Also disclosed is a method of fabricating the SOI device.
摘要翻译：绝缘体上半导体（SOI）器件。 SOi器件包括衬底，设置在衬底上的绝缘体层和设置在绝缘体层上的有源区。有源区域包括源极，漏极和设置在它们之间的主体。来源和身体形成突然或超破坏的源/体结。栅极设置在主体上以可操作地形成晶体管。植入区域在主体和漏极之间形成界面，通过倾斜的原子注入在朝向有源区域的方向上形成的注入区域和从栅极相对于垂直方向朝向漏极倾斜的角度形成注入区域，形成分级排水/身体结。还公开了一种制造SOI器件的方法。

4. 发明申请

US20140078817A1 INTEGRATED CIRCUITS WITH SRAM CELLS HAVING ADDITIONAL READ STACKS AND METHODS FOR THEIR FABRICATION 有权
标题翻译：具有附加读取堆栈的SRAM单元的集成电路及其制造方法
公开(公告)号：US20140078817A1
公开(公告)日：2014-03-20
申请号：US13617716
申请日：2012-09-14
申请人： Ralf van Bentum , Torsten Klick
发明人： Ralf van Bentum , Torsten Klick
IPC分类号： G11C11/419 , H01L21/265 , H01L21/60 , G11C7/12
CPC分类号： G11C11/4091 , G11C11/412 , H01L27/0207 , H01L27/1104
摘要： Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of SRAM cells in and on a semiconductor substrate, each of the plurality of SRAM cells including a read pull down transistor and a read pass gate transistor. First conductivity-determining impurity ions are implanted to establish a first threshold voltage in each of the read pull down transistors; and second conductivity-determining impurity ions are implanted to establish a second threshold voltage different than the first threshold voltage in each of the read pass gate transistors.
摘要翻译：提供了包括具有附加读取堆栈的SRAM单元及其制造方法的集成电路。根据一个实施例，用于制造这种集成电路的方法包括在半导体衬底中以及半导体衬底上形成多个SRAM单元，多个SRAM单元中的每一个包括读下拉晶体管和读通道晶体管。注入第一导电率确定杂质离子以在每个读下拉晶体管中建立第一阈值电压; 并且注入第二导电率确定杂质离子以在每个读通道晶体管中建立与第一阈值电压不同的第二阈值电压。

5. 发明授权

US08431455B2 Method of improving memory cell device by ion implantation 有权
标题翻译：通过离子注入改善记忆单元器件的方法
公开(公告)号：US08431455B2
公开(公告)日：2013-04-30
申请号：US13169360
申请日：2011-06-27
申请人： Ralf van Bentum , Nihar-Ranjan Mohapatra
发明人： Ralf van Bentum , Nihar-Ranjan Mohapatra
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/1104
摘要： Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer.
摘要翻译：本文公开了一种形成存储器件的方法。在一个示例中，该方法包括用第一类型的掺杂剂原子执行第一离子注入工艺以部分地形成用于下拉晶体管的延伸注入区域并且完全形成用于存储器件的通孔栅极晶体管的延伸注入区域，在执行第一离子注入工艺之后，形成掩模栅极晶体管的第一掩模层并使下拉晶体管进一步处理。该方法的结论是用第一种类型的掺杂剂原子进行第二离子注入工艺，以将另外的掺杂剂原子引入用于在第一离子注入工艺期间形成的下拉晶体管的延伸注入区域，同时屏蔽通过栅极晶体管与第一掩模层的第二离子注入工艺。

6. 发明授权

US08158486B2 Trench isolation structure having different stress 有权
标题翻译：具有不同应力的沟槽隔离结构
公开(公告)号：US08158486B2
公开(公告)日：2012-04-17
申请号：US11537809
申请日：2006-10-02
申请人： Ralf Van Bentum , Klaus Hempel , Roland Stejskal
发明人： Ralf Van Bentum , Klaus Hempel , Roland Stejskal
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76237 , H01L21/823412 , H01L29/7846
摘要： By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of an appropriate mask layer, which may provide a patterned optical response for a lamp-based or laser-based anneal process. Consequently, the intrinsic stress of isolation trenches may be specifically adapted to the requirements of circuit elements, such as N-channel transistors and P-channel transistors.
摘要翻译：通过局部加热具有不同退火条件的隔离沟槽，可以在不同的隔离沟槽中获得不同大小的固有应力。在一些说明性实施例中，可以基于合适的掩模层来实现不同的退火温度，其可以为基于灯或基于激光的退火工艺提供图案化的光学响应。因此，隔离沟槽的固有应力可以特别适用于诸如N沟道晶体管和P沟道晶体管的电路元件的要求。

7. 发明申请

US20070155122A1 TRENCH ISOLATION STRUCTURE HAVING DIFFERENT STRESS 有权
标题翻译：具有不同应力的高温隔离结构
公开(公告)号：US20070155122A1
公开(公告)日：2007-07-05
申请号：US11537809
申请日：2006-10-02
申请人： Ralf Van Bentum , Klaus Hempel , Roland Stejskal
发明人： Ralf Van Bentum , Klaus Hempel , Roland Stejskal
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76237 , H01L21/823412 , H01L29/7846
摘要： By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of an appropriate mask layer, which may provide a patterned optical response for a lamp-based or laser-based anneal process. Consequently, the intrinsic stress of isolation trenches may be specifically adapted to the requirements of circuit elements, such as N-channel transistors and P-channel transistors.
摘要翻译：通过局部加热具有不同退火条件的隔离沟槽，可以在不同的隔离沟槽中获得不同大小的固有应力。在一些说明性实施例中，可以基于合适的掩模层来实现不同的退火温度，其可以为基于灯或基于激光的退火工艺提供图案化的光学响应。因此，隔离沟槽的固有应力可以特别适用于诸如N沟道晶体管和P沟道晶体管的电路元件的要求。

8. 发明申请

US20050095796A1 Technique for forming a transistor having raised drain and source regions with a reduced number of process steps 有权
标题翻译：用于形成具有减少的工艺步骤数量的具有升高的漏极和源极区域的晶体管的技术
公开(公告)号：US20050095796A1
公开(公告)日：2005-05-05
申请号：US10891996
申请日：2004-07-15
申请人： Ralf van Bentum , Scott Luning , Thorsten Kammler
发明人： Ralf van Bentum , Scott Luning , Thorsten Kammler
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： By using sidewall spacers adjacent to a gate electrode structure both as an epitaxial growth mask and an implantation mask, the complexity of a conventional process flow for forming raised drain and source regions may be significantly reduced, thereby reducing production costs and enhancing yield by lowering the defect rate.
摘要翻译：通过使用与栅极电极结构相邻的侧壁间隔作为外延生长掩模和注入掩模，可以显着降低形成隆起的漏极和源极区域的常规工艺流程的复杂性，从而降低生产成本并通过降低缺陷率。

9. 发明申请

US20120329220A1 Method of Improving Memory Cell Device by Ion Implantation 有权
标题翻译：通过离子注入改善记忆单元器件的方法
公开(公告)号：US20120329220A1
公开(公告)日：2012-12-27
申请号：US13169360
申请日：2011-06-27
申请人： Ralf van Bentum , Nihar-Ranjan Mohapatra
发明人： Ralf van Bentum , Nihar-Ranjan Mohapatra
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L27/1104
摘要： Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer.
摘要翻译：本文公开了一种形成存储器件的方法。在一个示例中，该方法包括用第一类型的掺杂剂原子执行第一离子注入工艺以部分地形成用于下拉晶体管的延伸注入区域并且完全形成用于存储器件的通孔栅极晶体管的延伸注入区域，在执行第一离子注入工艺之后，形成掩模栅极晶体管的第一掩模层并使下拉晶体管进一步处理。该方法的结论是用第一种类型的掺杂剂原子进行第二离子注入工艺，以将另外的掺杂剂原子引入用于在第一离子注入工艺期间形成的下拉晶体管的延伸注入区域，同时屏蔽通过栅极晶体管与第一掩模层的第二离子注入工艺。

10. 发明授权

US07754555B2 Transistor having a channel with biaxial strain induced by silicon/germanium in the gate electrode 有权
标题翻译：晶体管具有在栅电极中由硅/锗引起的具有双轴应变的通道
公开(公告)号：US07754555B2
公开(公告)日：2010-07-13
申请号：US11674713
申请日：2007-02-14
申请人： Andreas Gehring , Ralf Van Bentum , Markus Lenski
发明人： Andreas Gehring , Ralf Van Bentum , Markus Lenski
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/823412 , H01L21/82345 , H01L21/823807 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7845 , H01L29/7848
摘要： By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.
摘要翻译：通过在栅电极中形成应力半导体材料，可以在沟道区域中诱发双轴拉伸应变，从而显着提高载流子迁移率。该概念可以有利地与额外的应变诱发源（例如在漏极和源极区域中的嵌入式应变半导体材料）结合，从而提供增强晶体管性能的潜力，而不会造成工艺复杂性。

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