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1. 发明授权

US09034744B2 Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material 有权
标题翻译：通过避免用于暴露占位符材料的抛光工艺，用于高k金属栅极堆叠的替代栅极方法
公开(公告)号：US09034744B2
公开(公告)日：2015-05-19
申请号：US12942200
申请日：2010-11-09
申请人： Ralf Richter , Jens Heinrich , Andy Wei
发明人： Ralf Richter , Jens Heinrich , Andy Wei
IPC分类号： H01L29/772 , H01L21/8238 , H01L21/768 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/76819 , H01L21/823807 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7843
摘要： In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.
摘要翻译：在替代栅极方法中，栅极电极结构的占位符材料的暴露可以基于蚀刻工艺来实现，从而避免引入与工艺相关的非均匀性，这通常与复杂的抛光工艺相关暴露占位符材料的顶面。在一些说明性实施例中，占位符材料可以通过基于牺牲掩模材料的蚀刻工艺曝光。

2. 发明授权

US08951907B2 Semiconductor devices having through-contacts and related fabrication methods 有权
标题翻译：具有通孔和相关制造方法的半导体器件
公开(公告)号：US08951907B2
公开(公告)日：2015-02-10
申请号：US12968068
申请日：2010-12-14
申请人： Ralf Richter , Jens Heinrich , Holger Schuehrer
发明人： Ralf Richter , Jens Heinrich , Holger Schuehrer
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/285 , H01L23/485
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76802 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact.
摘要翻译：提供了半导体器件结构和相关制造方法的装置。一种用于制造半导体器件结构的方法包括形成覆盖在与栅极结构相邻的半导体衬底中形成的掺杂区域的介电材料层，并在该介电材料层中形成导电接触。导电接触覆盖并电连接到掺杂区域。该方法继续通过形成覆盖导电接触的第二层介电材料，在覆盖导电接触的第二层中形成空隙区域，形成覆盖空隙区域的第三层电介质材料，以及在第三层中形成另一个空隙区域覆盖第二层中的空隙区域的至少一部分。该方法通过形成填充两个空隙区域以接触导电触点的导电材料而继续。

3. 发明授权

US08697584B2 Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device 有权
标题翻译：通过在半导体器件中的双应力衬垫上方使用附加层来增强N沟道晶体管的晶体管性能
公开(公告)号：US08697584B2
公开(公告)日：2014-04-15
申请号：US12017175
申请日：2008-01-21
申请人： Ralf Richter , Andy Wei , Roman Boschke
发明人： Ralf Richter , Andy Wei , Roman Boschke
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L29/7843
摘要： By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.
摘要翻译：通过在构成不同固有应力的介电衬垫的图案之后形成诸如氮化硅的附加电介质材料，可以获得N沟道晶体管的性能的显着提高，同时基本上不会导致P沟道晶体管的性能损失。

4. 发明申请

US20140048912A1 COMPRESSIVE STRESS TRANSFER IN AN INTERLAYER DIELECTRIC OF A SEMICONDUCTOR DEVICE BY PROVIDING A BI-LAYER OF SUPERIOR ADHESION AND INTERNAL STRESS 有权
标题翻译：通过提供超级粘合和内应力的双层来在半导体器件的中间层电介质中的压应力传递
公开(公告)号：US20140048912A1
公开(公告)日：2014-02-20
申请号：US13588460
申请日：2012-08-17
申请人： Joerg Hohage , Hartmut Ruelke , Ralf Richter
发明人： Joerg Hohage , Hartmut Ruelke , Ralf Richter
IPC分类号： H01L21/31 , H01L29/06
CPC分类号： H01L21/76832 , C23C16/345 , C23C16/45523 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/76834 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
摘要翻译：本公开提供了制造技术和半导体器件，其中可以基于涉及沉积介电双层系统的应力机制来增强P沟道晶体管的性能。与常规策略相反，可以在粘附层在无等离子体的工艺气氛中沉积之前进行另外的预处理，从而能够减小粘合层的厚度和随后的顶层的更高的内应力水平。

5. 发明授权

US08541885B2 Technique for enhancing transistor performance by transistor specific contact design 有权
标题翻译：通过晶体管特定接触设计增强晶体管性能的技术
公开(公告)号：US08541885B2
公开(公告)日：2013-09-24
申请号：US13107515
申请日：2011-05-13
申请人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
发明人： Martin Gerhardt , Ralf Richter , Thomas Feudel , Uwe Griebenow
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823871 , H01L23/485 , H01L29/41758 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
摘要翻译：通过局部地适应接触结构的尺寸和/或密度，例如，在单个晶体管内或以更全球化的方式，可以增加先进半导体器件的整体性能。因此，可以考虑接触结构和局部器件特性之间的相互作用。另一方面，可以保持与常规工艺策略的高度兼容性。

6. 发明授权

US08497554B2 Semiconductor device comprising metal gate structures formed by a replacement gate approach and efuses including a silicide 有权
标题翻译：半导体器件包括通过替换栅极方法形成的金属栅极结构和包括硅化物的熔点
公开(公告)号：US08497554B2
公开(公告)日：2013-07-30
申请号：US12942506
申请日：2010-11-09
申请人： Andy Wei , Jens Heinrich , Ralf Richter
发明人： Andy Wei , Jens Heinrich , Ralf Richter
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L27/0617 , H01L27/0629 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In a replacement gate approach for forming high-k metal gate electrode structures, electronic fuses may be provided on the basis of a semiconductor material in combination with a metal silicide by using a recessed surface topography and/or a superior selectivity of the metal silicide material during the replacement gate process. For example, in some illustrative embodiments, electronic fuses may be provided in a recessed portion of an isolation region, thereby avoiding the removal of the semiconductor material when replacing the semiconductor material of the gate electrode structures with a metal-containing electrode material. Consequently, the concept of well-established semiconductor-based electronic fuses may be applied together with sophisticated replacement gate structures of transistors.
摘要翻译：在用于形成高k金属栅电极结构的替代栅极方法中，可以通过使用凹陷表面形貌和/或金属硅化物材料的优异选择性，基于半导体材料与金属硅化物的组合来提供电子熔丝在替换门过程中。例如，在一些说明性实施例中，电子熔丝可以设置在隔离区域的凹陷部分中，从而避免了当用含金属的电极材料替换栅电极结构的半导体材料时去除半导体材料。因此，已经确立的基于半导体的电子熔丝的概念可以与晶体管的复杂的替代栅极结构一起应用。

7. 发明授权

US08492269B2 Hybrid contact structure with low aspect ratio contacts in a semiconductor device 有权
标题翻译：在半导体器件中具有低纵横比接触的混合接触结构
公开(公告)号：US08492269B2
公开(公告)日：2013-07-23
申请号：US13234529
申请日：2011-09-16
申请人： Jens Heinrich , Ralf Richter , Torsten Huisinga , Kai Frohberg
发明人： Jens Heinrich , Ralf Richter , Torsten Huisinga , Kai Frohberg
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76877 , H01L23/485 , H01L23/53238 , H01L23/53257 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal.
摘要翻译：在复杂的半导体器件中，通过提供混合接触元件，对于给定的接触构型可以实现优异的接触电阻率，其中至少一部分可由高导电材料（例如铜）构成。为此，可以使用诸如钨的良好接触材料作为缓冲材料，以便在沉积高导电性金属时保持敏感器件区域的完整性。

8. 发明授权

US08445378B2 Method of manufacturing a CMOS device including molecular storage elements in a via level 有权
标题翻译：制造包括通孔级分子存储元件的CMOS器件的方法
公开(公告)号：US08445378B2
公开(公告)日：2013-05-21
申请号：US12839455
申请日：2010-07-20
申请人： Stephan Kronholz , Markus Lenski , Ralf Richter
发明人： Stephan Kronholz , Markus Lenski , Ralf Richter
IPC分类号： H01L21/768
CPC分类号： H01L27/281 , G11C13/0014 , G11C13/0016 , H01L51/0003 , H01L51/0591
摘要： Memory cells in integrated circuit devices may be formed on the basis of functional molecules which may be positioned within via openings on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a “molecular” level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the like.
摘要翻译：可以基于功能分子形成集成电路器件中的存储器单元，功能分子可以基于合适的图案化技术而定位在通孔开口内，该技术也可用于形成基于半导体的集成电路。因此，可以在“分子”水平上形成记忆单元，而不需要非常复杂的图案化方案，例如电子束光刻等。

9. 发明授权

US08440561B2 Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules 有权
标题翻译：三维半导体器件包括基于功能分子的管芯间连接
公开(公告)号：US08440561B2
公开(公告)日：2013-05-14
申请号：US12844263
申请日：2010-07-27
申请人： Stephan Kronholz , Markus Lenski , Ralf Richter
发明人： Stephan Kronholz , Markus Lenski , Ralf Richter
IPC分类号： H01L27/14
CPC分类号： H01L23/5226 , H01L21/8221 , H01L23/53276 , H01L27/0688 , H01L2924/00011 , H01L2924/00013 , H01L2924/0002 , H01L2924/01013 , H01L2924/01016 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/80001
摘要： In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.
摘要翻译：在堆叠式芯片配置中，基于功能分子建立“芯片间”连接，从而在不同半导体芯片之间提供快速且空间有效的通信。

10. 发明申请

US20130089985A1 Enhancing Transistor Performance by Reducing Exposure to Oxygen Plasma in a Dual Stress Liner Approach 有权
标题翻译：通过在双重应力衬垫方法中减少暴露于氧等离子体来提高晶体管性能
公开(公告)号：US20130089985A1
公开(公告)日：2013-04-11
申请号：US13253210
申请日：2011-10-05
申请人： Ronald NAUMANN , Volker GRIMM , Andrey ZAKHAROV , Ralf RICHTER
发明人： Ronald NAUMANN , Volker GRIMM , Andrey ZAKHAROV , Ralf RICHTER
IPC分类号： H01L21/31
CPC分类号： H01L21/31138 , H01L21/0206 , H01L21/823807 , H01L29/7848
摘要： When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.
摘要翻译：当在不同导电类型的晶体管上形成应变诱导介电材料层时，至少一种应变诱导电介质材料的图案化可以基于氧等离子体中氟物质的负面影响的工艺顺序避免或至少显着地抑制去除抗蚀剂掩模。例如，可以施加基本上无氧的等离子体工艺来去除抗蚀剂材料。

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