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1. 发明授权

US08575648B2 Silicon carbide semiconductor device and method of manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US08575648B2
公开(公告)日：2013-11-05
申请号：US12976116
申请日：2010-12-22
申请人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Naohiro Sugiyama
发明人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Naohiro Sugiyama
IPC分类号： H01L29/423 , H01L21/337
CPC分类号： H01L29/0847 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.
摘要翻译：具有JFET或MOSFET的碳化硅半导体器件包括半导体衬底和沟槽。半导体衬底具有碳化硅衬底，碳化硅衬底上的漂移层，漂移层上的第一栅极区域和第一栅极区域上的源极区域。沟槽具有纵向方向的带状，并通过穿透源极区域和第一栅极区域而到达漂移层。在沟道层上填充沟道层和第二栅极区域。源极区域不位于沟槽的纵向方向的端部。

2. 发明授权

US08604540B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604540B2
公开(公告)日：2013-12-10
申请号：US12956152
申请日：2010-11-30
申请人： Rajesh Kumar Malhan , Naohiro Sugiyama , Yuuichi Takeuchi
发明人： Rajesh Kumar Malhan , Naohiro Sugiyama , Yuuichi Takeuchi
IPC分类号： H01L29/66 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/8128
摘要： A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.
摘要翻译：具有JFET，MESFET或MOSFET的宽带隙半导体器件主要包括半导体衬底，第一导电类型半导体层和第一导电型沟道层。半导体层形成在基板的主表面上。在半导体层中以半导体层被分成源极区和漏极区的方式形成凹部。凹部具有由基板的主表面和由半导体层限定的侧壁限定的底部。沟道层的杂质浓度低于半导体层的杂质浓度。沟槽层通过外延生长形成在凹部的底部和侧壁上。

3. 发明申请

US20110156052A1 Semiconductor device having JFET and method for manufacturing the same 审中-公开
标题翻译：具有JFET的半导体器件及其制造方法
公开(公告)号：US20110156052A1
公开(公告)日：2011-06-30
申请号：US12926894
申请日：2010-12-16
申请人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Naohiro Sugiyama
发明人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Naohiro Sugiyama
IPC分类号： H01L29/24 , H01L29/80 , H01L21/337
CPC分类号： H01L29/808 , H01L29/045 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region.
摘要翻译：具有JFET的半导体器件包括：由半绝缘半导体材料制成的衬底; 在所述基板的表面部分中的栅极区域; 设置在栅区上并与其接触的沟道区; 源极区域和漏极区域，分别设置在栅极区域的两侧，以夹持沟道区域; 源极，与源极电耦合; 漏极，与漏极区电耦合; 以及与栅极区域电耦合的栅电极。源极区域和漏极区域中的每一个的杂质浓度高于沟道区域的杂质浓度。

4. 发明申请

US20110133211A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110133211A1
公开(公告)日：2011-06-09
申请号：US12956152
申请日：2010-11-30
申请人： Rajesh Kumar MALHAN , Naohiro Sugiyama , Yuuichi Takeuchi
发明人： Rajesh Kumar MALHAN , Naohiro Sugiyama , Yuuichi Takeuchi
IPC分类号： H01L29/161 , H01L29/812 , H01L29/78 , H01L29/80 , H01L21/337 , H01L21/338 , H01L21/336
CPC分类号： H01L29/808 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/8128
摘要： A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.
摘要翻译：具有JFET，MESFET或MOSFET的宽带隙半导体器件主要包括半导体衬底，第一导电类型半导体层和第一导电型沟道层。半导体层形成在基板的主表面上。在半导体层中以半导体层被分成源极区和漏极区的方式形成凹部。凹部具有由基板的主表面和由半导体层限定的侧壁限定的底部。沟道层的杂质浓度低于半导体层的杂质浓度。沟槽层通过外延生长形成在凹部的底部和侧壁上。

5. 发明授权

US07241694B2 Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate 有权
标题翻译：一种在碳化硅半导体衬底中制造具有沟槽的半导体器件的方法
公开(公告)号：US07241694B2
公开(公告)日：2007-07-10
申请号：US11105587
申请日：2005-04-14
申请人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L21/18 , H01L21/302 , H01L21/308
CPC分类号： H01L29/045 , H01L29/66068 , H01L29/7828 , H01L29/8083
摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.
摘要翻译：一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除比1600℃

6. 发明授权

US08274086B2 Wide band gap semiconductor device including junction field effect transistor 有权
标题翻译：宽带隙半导体器件包括结场效应晶体管
公开(公告)号：US08274086B2
公开(公告)日：2012-09-25
申请号：US12458968
申请日：2009-07-28
申请人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Jeremy Rashid
发明人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Jeremy Rashid
IPC分类号： H01L29/15 , H01L31/0256
CPC分类号： H01L29/8083 , H01L29/063 , H01L29/0692 , H01L29/6609 , H01L29/66325 , H01L29/8611 , H01L29/872
摘要： A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
摘要翻译：宽带隙半导体器件具有晶体管单元区域，二极管形成区域，位于晶体管单元区域和二极管形成区域之间的电场弛豫区域以及围绕晶体管单元区域和二极管形成区域的外围区域。在晶体管单元区域中，设置结型场效应晶体管。在二极管形成区域中，设置二极管。在电场弛豫区域中，设置隔离部。隔离部分包括分隔晶体管单元区域和二极管形成区域的沟槽，设置在沟槽的内壁上的第一导电类型层和设置在第一导电类型层的表面上的第二导电类型层以填补沟槽。第一导电型层和第二导电型层提供PN结。

7. 发明申请

US20100025693A1 Wide band gap semiconductor device including junction field effect transistor 有权
标题翻译：宽带隙半导体器件包括结场效应晶体管
公开(公告)号：US20100025693A1
公开(公告)日：2010-02-04
申请号：US12458968
申请日：2009-07-28
申请人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Jeremy Rashid
发明人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Jeremy Rashid
IPC分类号： H01L29/772 , H01L29/02
CPC分类号： H01L29/8083 , H01L29/063 , H01L29/0692 , H01L29/6609 , H01L29/66325 , H01L29/8611 , H01L29/872
摘要： A wide band gap semiconductor device has a transistor cell region, a diode forming region, an electric field relaxation region located between the transistor cell region and the diode forming region, and an outer peripheral region surrounding the transistor cell region and the diode forming region. In the transistor cell region, a junction field effect transistor is disposed. In the diode forming region, a diode is disposed. In the electric field relaxation region, an isolating part is provided. The isolating part includes a trench dividing the transistor cell region and the diode forming region, a first conductivity-type layer disposed on an inner wall of the trench, and a second conductivity-type layer disposed on a surface of the first conductivity-type layer so as to fill the trench. The first conductivity-type layer and the second conductivity-type layer provide a PN junction.
摘要翻译：宽带隙半导体器件具有晶体管单元区域，二极管形成区域，位于晶体管单元区域和二极管形成区域之间的电场弛豫区域以及围绕晶体管单元区域和二极管形成区域的外围区域。在晶体管单元区域中，设置结型场效应晶体管。在二极管形成区域中，设置二极管。在电场弛豫区域中，设置隔离部。隔离部分包括分隔晶体管单元区域和二极管形成区域的沟槽，设置在沟槽的内壁上的第一导电类型层和设置在第一导电类型层的表面上的第二导电类型层以填补沟槽。第一导电型层和第二导电型层提供PN结。

8. 再颁专利

USRE43840E1 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：USRE43840E1
公开(公告)日：2012-12-04
申请号：US12926030
申请日：2010-10-21
申请人： Mitsuhiro Kataoka , Yuuichi Takeuchi , Masami Naito , Rajesh Kumar , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Mitsuhiro Kataoka , Yuuichi Takeuchi , Masami Naito , Rajesh Kumar , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L31/0312
CPC分类号： H01L29/66068 , H01L29/045 , H01L29/1608 , H01L29/8083
摘要： A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.
摘要翻译：碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。在沟槽的内表面上形成SiC外延层。

9. 发明申请

US20060273323A1 Semiconductor device having SiC substrate and method for manufacturing the same 审中-公开
标题翻译：具有SiC衬底的半导体器件及其制造方法
公开(公告)号：US20060273323A1
公开(公告)日：2006-12-07
申请号：US11448138
申请日：2006-06-07
申请人： Takeo Yamamoto , Malhan Kumar , Yuuichi Takeuchi , Konstantin Vassilevski , Nicholas Wright
发明人： Takeo Yamamoto , Malhan Kumar , Yuuichi Takeuchi , Konstantin Vassilevski , Nicholas Wright
IPC分类号： H01L31/0312
CPC分类号： H01L21/0485 , H01L29/1608
摘要： A semiconductor device includes: a SiC substrate; a silicide layer disposed on the SiC substrate; and a carbide layer disposed on the silicide layer. The silicide layer includes a first metal, and the carbide layer includes a second metal. The first metal is Ni or Ni alloy, and the second metal is Ti, Ta or W. The device provides excellent ohmic contact and high quality surface metallization construction.
摘要翻译：半导体器件包括：SiC衬底; 设置在所述SiC衬底上的硅化物层; 以及设置在硅化物层上的碳化物层。硅化物层包括第一金属，并且碳化物层包括第二金属。第一种金属是Ni或Ni合金，第二种金属是Ti，Ta或W.该器件提供了优异的欧姆接触和高品质的表面金属化结构。

10. 发明授权

US07078329B2 Method of manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US07078329B2
公开(公告)日：2006-07-18
申请号：US10824497
申请日：2004-04-15
申请人： Takeshi Endou , Yuuichi Takeuchi
发明人： Takeshi Endou , Yuuichi Takeuchi
IPC分类号： H01L21/283 , H01L31/0312
CPC分类号： H01L29/66068 , H01L21/0485 , H01L29/1608 , H01L29/7828 , Y10S438/931
摘要： An insulating film (2) is formed on a semiconductor substrate (1) formed of silicon carbide. A contact hole (3) is formed in the insulating film (2) to expose a part of the upper surface of the semiconductor substrate (1). Then, nickel (Ni) (4′) is formed above the semiconductor substrate (1). Subsequently, the semiconductor substrate (1) is subjected to a heat treatment, whereby the contact portion of nickel (4′) chemically bonds with the semiconductor substrate (1) to become an alloy layer (4) of silicon carbide and nickel. Nickel (4′) on the insulating film (2) is selectively removed by etching liquid for dissolving the nickel.
摘要翻译：在由碳化硅形成的半导体衬底（1）上形成绝缘膜（2）。在绝缘膜（2）中形成接触孔（3）以暴露半导体衬底（1）的上表面的一部分。然后，在半导体衬底（1）的上方形成镍（Ni）（4'）。随后，对半导体衬底（1）进行热处理，由此镍（4'）的接触部分与半导体衬底（1）化学键合成为碳化硅和镍的合金层（4）。通过蚀刻用于溶解镍的液体来选择性地除去绝缘膜（2）上的镍（4'）。

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