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1. 发明授权

US07241694B2 Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate 有权
标题翻译：一种在碳化硅半导体衬底中制造具有沟槽的半导体器件的方法
公开(公告)号：US07241694B2
公开(公告)日：2007-07-10
申请号：US11105587
申请日：2005-04-14
申请人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Yuuichi Takeuchi , Rajesh Kumar Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L21/18 , H01L21/302 , H01L21/308
CPC分类号： H01L29/045 , H01L29/66068 , H01L29/7828 , H01L29/8083
摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.
摘要翻译：一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除比1600℃

2. 发明申请

US20050233539A1 Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate 有权
标题翻译：一种在碳化硅半导体衬底中制造具有沟槽的半导体器件的方法
公开(公告)号：US20050233539A1
公开(公告)日：2005-10-20
申请号：US11105587
申请日：2005-04-14
申请人： Yuuichi Takeuchi , Rajesh Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Yuuichi Takeuchi , Rajesh Malhan , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： C30B23/02 , H01L21/04 , H01L21/306 , H01L21/337 , H01L21/76 , H01L29/04 , H01L29/24 , H01L29/78 , H01L29/808
CPC分类号： H01L29/045 , H01L29/66068 , H01L29/7828 , H01L29/8083
摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.
摘要翻译：一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除比1600℃

3. 再颁专利

USRE43840E1 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：USRE43840E1
公开(公告)日：2012-12-04
申请号：US12926030
申请日：2010-10-21
申请人： Mitsuhiro Kataoka , Yuuichi Takeuchi , Masami Naito , Rajesh Kumar , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Mitsuhiro Kataoka , Yuuichi Takeuchi , Masami Naito , Rajesh Kumar , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L31/0312
CPC分类号： H01L29/66068 , H01L29/045 , H01L29/1608 , H01L29/8083
摘要： A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.
摘要翻译：碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。在沟槽的内表面上形成SiC外延层。

4. 发明授权

US06853006B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US06853006B2
公开(公告)日：2005-02-08
申请号：US10630978
申请日：2003-07-31
申请人： Mitsuhiro Kataoka , Yuuichi Takeuchi , Masami Naito , Rajesh Kumar , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Mitsuhiro Kataoka , Yuuichi Takeuchi , Masami Naito , Rajesh Kumar , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L29/80 , H01L21/04 , H01L21/337 , H01L29/04 , H01L29/24 , H01L29/808 , H01L31/312
CPC分类号： H01L29/66068 , H01L29/045 , H01L29/1608 , H01L29/8083
摘要： A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.
摘要翻译：碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。在沟槽的内表面上形成SiC外延层。

5. 发明申请

US20090261362A1 4H-POLYTYPE GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE ON A 4H-POLYTYPE SUBSTRATE 审中-公开
标题翻译： 4H-多晶型氮化镓基半导体器件在4H-多晶基片上
公开(公告)号：US20090261362A1
公开(公告)日：2009-10-22
申请号：US12496271
申请日：2009-07-01
申请人： Tetsuzo UEDA , Tsunenobu Kimoto , Hiroyuki Matsunami , Jun Suda , Norio Onojima
发明人： Tetsuzo UEDA , Tsunenobu Kimoto , Hiroyuki Matsunami , Jun Suda , Norio Onojima
IPC分类号： H01L33/00
CPC分类号： H01L21/02082 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L33/18 , H01L33/32
摘要： 4H—InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H—AlN or 4H—AlGaN on (11-20) a-face 4H—SiC substrates. Typically, non polar 4H—AlN is grown on 4H—SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectronic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes (LEDs) using conductive 4H—AlGaN interlayer on conductive 4H—SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors. The details of the epitaxial growth s and the processing procedures for the non-polar III-V nitride devices on the non-polar SiC substrates are also disclosed.
摘要翻译：在（11-20）a面4H-SiC衬底上的4H-AlN或4H-AlGaN上形成4H-InGaAlN合金基非极性面上的光电子和电子器件。通常，非极性4H-AlN通过分子束外延（MBE）在4H-SiC（11-20）上生长。随后，通过用于所有层的4H-多型金属有机化学气相沉积（MOCVD）生长III-V族氮化物器件层。由于自发和压电极化，非极性器件不包含任何内置的电场。由于电子和空穴在量子阱中没有空间分离，非极性面上的光电器件表现出较短的发射波长的发射效率。在导电4H-SiC衬底上使用导电4H-AlGaN夹层的激光器和发光二极管（LED）的垂直器件配置使芯片尺寸和串联电阻更小。这种电场的消除也提高了高速和高功率晶体管的性能。还公开了非极性SiC衬底上的非极性III-V族氮化物器件的外延生长细节和处理步骤。

6. 发明申请

US20080277696A1 Lateral Junction Field Effect Transistor and Method of Manufacturing The Same 有权
标题翻译：横向结场效应晶体管及其制造方法
公开(公告)号：US20080277696A1
公开(公告)日：2008-11-13
申请号：US12179320
申请日：2008-07-24
申请人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L29/808
CPC分类号： H01L29/0634 , H01L29/1058 , H01L29/1066 , H01L29/42316 , H01L29/66893 , H01L29/808
摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
摘要翻译：横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及具有与第一栅极电极层相同的电位。因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

7. 发明申请

US20050218414A1 4H-polytype gallium nitride-based semiconductor device on a 4H-polytype substrate 审中-公开
标题翻译： 4H型多晶氮化镓基半导体器件
公开(公告)号：US20050218414A1
公开(公告)日：2005-10-06
申请号：US10812416
申请日：2004-03-30
申请人： Tetsuzo Ueda , Tsunenobu Kimoto , Hiroyuki Matsunami , Jun Suda , Norio Onojima
发明人： Tetsuzo Ueda , Tsunenobu Kimoto , Hiroyuki Matsunami , Jun Suda , Norio Onojima
IPC分类号： H01L29/26 , H01L21/02 , H01L21/20 , H01L21/338 , H01L29/778 , H01L29/812 , H01L33/18 , H01L33/32 , H01S5/323 , H01L33/00
CPC分类号： H01L21/02082 , H01L21/02378 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L33/18 , H01L33/32
摘要： 4H-InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H-AlN or 4H-AlGaN on (11-20) a-face 4H-SiC substrates. Typically, non polar 4H-AlN is grown on 4H-SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectonic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes(LEDs) using conductive 4H-AlGaN interlayer on conductive 4H-SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors. The details of the epitaxial growth s and the processing procedures for the non-polar III-V nitride devices on the non-polar SiC substrates are also disclosed.
摘要翻译：在（11-20）a面4H-SiC衬底上的4H-AlN或4H-AlGaN上形成4H-InGaAlN合金基非极性面上的光电子和电子器件。通常，非极性4H-AlN通过分子束外延（MBE）在4H-SiC（11-20）上生长。随后，通过用于所有层的4H-多型金属有机化学气相沉积（MOCVD）生长III-V族氮化物器件层。由于自发和压电极化，非极性器件不包含任何内置的电场。由于电子和空穴在量子阱中空间不分开，非极性面上的光电子器件表现出更高的发射效率，发射波长更短。在导电4H-SiC衬底上使用导电4H-AlGaN夹层的激光器和发光二极管（LED）的垂直器件配置使芯片尺寸和串联电阻更小。这种电场的消除也提高了高速和高功率晶体管的性能。还公开了非极性SiC衬底上的非极性III-V族氮化物器件的外延生长细节和处理步骤。

8. 发明授权

US06870189B1 Pinch-off type vertical junction field effect transistor and method of manufacturing the same 失效
标题翻译：夹断型垂直结场效应晶体管及其制造方法
公开(公告)号：US06870189B1
公开(公告)日：2005-03-22
申请号：US10168265
申请日：2000-09-11
申请人： Shin Harada , Kenichi Hirotsu , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Shin Harada , Kenichi Hirotsu , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L21/337 , H01L29/24 , H01L29/772 , H01L29/808 , H01L31/0312 , H01L29/80 , H01L31/112
CPC分类号： H01L29/0843 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/66901 , H01L29/66909 , H01L29/7722 , H01L29/808 , H01L29/8083
摘要： A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain. A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region.
摘要翻译：提供了一种结型场效应晶体管（JFET），其具有能够以低损耗工作并且几乎没有变化的高电压电阻，高电流切换操作。该JFET设置有设置在半导体衬底的表面上的第二导电类型的栅极区域（2），第一导电类型的源极区域（1），第一导电类型的沟道区域（10）源极区域，邻接栅极区域并限制沟道区域的第二导电类型的约束区域（5），设置在反面上的第一导电类型的漏极区域（3）和漂移区域（4）的第一导电类型，其连续地位于从通道到漏极的衬底的厚度方向上。漂移区域和沟道区域中的第一导电类型的杂质的浓度低于源极区域和漏极区域中的第一导电类型的杂质浓度和第二导电类型的杂质浓度在限制区域。

9. 发明授权

US06660084B1 Sic single crystal and method for growing the same 有权
标题翻译： Sic单晶和生长方法相同
公开(公告)号：US06660084B1
公开(公告)日：2003-12-09
申请号：US10069503
申请日：2002-02-27
申请人： Hiromu Shiomi , Tsunenobu Kimoto , Hiroyuki Matsunami
发明人： Hiromu Shiomi , Tsunenobu Kimoto , Hiroyuki Matsunami
IPC分类号： C30B2502
CPC分类号： C30B23/00 , C30B23/02 , C30B29/36
摘要： A method of growing a 4H-poly type SiC single crystal 40, characterized in that the 4H-poly type SiC single crystal 40 is grown on a seed crystal 30 comprised of an SiC single crystal where a {03-38} plane 30u or a plane which is inclined at off angle &agr;, within about 10°, with respect to the {03-38} plane, is exposed.
摘要翻译：一种生长4H-多晶型SiC单晶40的方法，其特征在于，4H-多晶型SiC单晶40在由SiC单晶构成的晶种30上生长，其中{03-38}面30u或相对于{03-38}平面倾斜偏角α在约10°内的平面被暴露。

10. 发明授权

US07671388B2 Lateral junction field effect transistor and method of manufacturing the same 有权
公开(公告)号：US07671388B2
公开(公告)日：2010-03-02
申请号：US12552212
申请日：2009-09-01
申请人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
发明人： Kazuhiro Fujikawa , Shin Harada , Kenichi Hirotsu , Satoshi Hatsukawa , Takashi Hoshino , Hiroyuki Matsunami , Tsunenobu Kimoto
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L29/1058 , H01L29/1066 , H01L29/42316 , H01L29/66893 , H01L29/808
摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

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