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1. 发明授权

US06849909B1 Method and apparatus for weak inversion mode MOS decoupling capacitor 失效
标题翻译：弱反转模式MOS去耦电容器的方法和装置
公开(公告)号：US06849909B1
公开(公告)日：2005-02-01
申请号：US09677698
申请日：2000-09-28
申请人： Rajendran Nair , Siva G. Narendra , Tanay Karnik , Vivek K. De
发明人： Rajendran Nair , Siva G. Narendra , Tanay Karnik , Vivek K. De
IPC分类号： H01L27/08 , H01L31/119 , H01L29/088 , H01L29/90
CPC分类号： H01L27/0811 , Y10S257/901
摘要： A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.
摘要翻译：描述了用于提供弱反型模式金属氧化物半导体（MOS）去耦电容器的方法和装置。在一个实施例中，增强型p沟道MOS（PMOS）晶体管由其功能与常用功能不同的栅极材料构成。在一个示例性实施方案中，使用铂硅酸盐（PtSi）。在替代实施例中，可以通过修改衬底的掺杂剂水平来改变PMOS晶体管的阈值电压。在任一实施例中，晶体管的平带幅度偏移用于构造晶体管的材料的变化。当这种晶体管与连接到正电源电压的栅极引线连接，而其他引线连接到负（接地）电源电压时，会产生改进的去耦电容。

2. 发明授权

US06448840B2 Adaptive body biasing circuit and method 失效
标题翻译：自适应体偏置电路及方法
公开(公告)号：US06448840B2
公开(公告)日：2002-09-10
申请号：US09452080
申请日：1999-11-30
申请人： James T. Kao , Vivek K. De , Siva G. Narendra , Rajendran Nair
发明人： James T. Kao , Vivek K. De , Siva G. Narendra , Rajendran Nair
IPC分类号： H03K301
CPC分类号： H01L27/0222 , H03K17/145 , H03K2217/0018
摘要： An adaptive body bias circuit forward or reverse biases bodies of transistors within a compensated circuit as a result of measured parameters of an integrated circuit. The adaptive body bias circuit includes a matched circuit that includes a replica of a signal path within the compensated circuit. The phase of a clock signal at the input to the matched circuit is compared to a phase of a delayed clock signal at the output of the matched circuit. When the delay through the matched circuit varies about one period of the clock signal, a non-zero error value is produced. A bias voltage is generated as a function of the error value, and the bias voltage is applied to the compensated circuit as well as the matched circuit. Integrated circuits can include many adaptive body bias circuits. Bias values can be stored in memories for later use, and bias values within memories can be updated periodically to compensate the circuit over time.
摘要翻译：作为集成电路的测量参数的结果，自适应体偏置电路正向或反向偏置补偿电路内的晶体管本体。自适应体偏置电路包括匹配电路，其包括补偿电路内的信号路径的副本。将匹配电路的输入端的时钟信号的相位与匹配电路输出端的延迟时钟信号的相位进行比较。当通过匹配电路的延迟在时钟信号的一个周期上变化时，产生非零误差值。产生偏置电压作为误差值的函数，并且偏置电压被施加到补偿电路以及匹配电路。集成电路可以包括许多自适应体偏置电路。偏置值可以存储在存储器中以供以后使用，并且周期性地更新存储器内的偏置值以补偿电路随时间变化。

3. 发明授权

US06828638B2 Decoupling capacitors for thin gate oxides 有权
标题翻译：薄栅氧化物去耦电容器
公开(公告)号：US06828638B2
公开(公告)日：2004-12-07
申请号：US09469406
申请日：1999-12-22
申请人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
发明人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
IPC分类号： H01L2976
CPC分类号： H01L27/0805 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
摘要翻译：在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。可以使用各种构造，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。电源电压可能比平带电压具有更大的绝对值。

4. 发明授权

US06552887B1 Voltage dependent capacitor configuration for higher soft error rate tolerance 有权
标题翻译：电压相关电容器配置，用于更高的软错误率容差
公开(公告)号：US06552887B1
公开(公告)日：2003-04-22
申请号：US09608457
申请日：2000-06-29
申请人： Tanay Karnik , Rajendran Nair , Vivek K. De
发明人： Tanay Karnik , Rajendran Nair , Vivek K. De
IPC分类号： G11C1140
CPC分类号： G11C5/005 , G11C11/401 , H01L27/0808
摘要： A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.
摘要翻译：公开了一种用于在集成电路中提供软错误率容限的电压相关电容器。在一个实施例中，使用并联n-p电压依赖电容器来保护节点免受噪声。在另一个实施例中，使用nFET-nWell电压相关电容器来提供具有减小的面积的软误差容限电容器。

5. 发明授权

US06456133B1 Duty cycle control loop 失效
标题翻译：占空比控制回路
公开(公告)号：US06456133B1
公开(公告)日：2002-09-24
申请号：US09752250
申请日：2000-12-28
申请人： Rajendran Nair , Chantal Wright , Stephen Mooney , Siva G. Narendra
发明人： Rajendran Nair , Chantal Wright , Stephen Mooney , Siva G. Narendra
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： An output circuit generates an output signal. The output signal has a duty cycle from an input signal. A level extractor couple to the output circuit to extract a direct current (DC) level from the output signal. The DC level is a representative of the duty cycle. An integrator couple to the level extractor to integrate the DC level. The integrator generates a current control signal to adjust the duty cycle.
摘要翻译：输出电路产生输出信号。输出信号具有来自输入信号的占空比。电平提取器耦合到输出电路以从输出信号提取直流（DC）电平。直流电平是占空比的代表。积分器耦合到级别提取器以集成直流电平。积分器产生电流控制信号以调整占空比。

6. 发明授权

US06229357B1 Frequency divider and method 有权
标题翻译：分频器和方法
公开(公告)号：US06229357B1
公开(公告)日：2001-05-08
申请号：US09388562
申请日：1999-09-02
申请人： Rajendran Nair , Siva G. Narendra
发明人： Rajendran Nair , Siva G. Narendra
IPC分类号： H03B1900
CPC分类号： H03K3/037
摘要： A frequency divider includes a pulse generator, a latch with differential outputs, and switches responsive to the state of the latch. The latch changes logical state in response to signal pulses produced by the pulse generator. The signal pulses are produced by the pulse generator in response to rising edges of an input signal applied to the pulse generator. A first output alignment circuit provides additional drive strength to a first of the differential outputs when it is transitioning high. A second output alignment circuit provides additional drive strength to a second of the differential outputs when it is transitioning high.
摘要翻译：分频器包括脉冲发生器，具有差分输出的锁存器和响应于锁存器状态的开关。锁存器响应脉冲发生器产生的信号脉冲改变逻辑状态。响应于施加到脉冲发生器的输入信号的上升沿，由脉冲发生器产生信号脉冲。当第一输出对准电路转变为高电平时，第一差分输出端提供额外的驱动强度。当第二输出对准电路转变为高电平时，向第二差分输出端提供额外的驱动强度。

7. 发明授权

US08563865B2 Flat wire shielded pair and cable 失效
标题翻译：扁平线屏蔽对和电缆
公开(公告)号：US08563865B2
公开(公告)日：2013-10-22
申请号：US13200974
申请日：2011-10-06
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H01B11/00 , H01B7/18
CPC分类号： H01B7/0876
摘要： Novel shielded flat wire pair and cable implement flat, smooth conductors coated with insulation bonded together, providing rectangular cross-sections and equidistant, smooth surfaces for high frequency signal current flow. Flat wire pairs with conductive covers and symmetrically placed shield conductors in grooves between flat wires minimize intra-pair signal flow skew. Shielded flat wire pairs are placed within a cable assembly with adjacent wire pairs oriented orthogonally, minimizing crosstalk and rendering crosstalk common-mode. Such orientation of flat wire pairs is assisted by an internal separator, which may be electrically conductive and grounded providing enhanced pair to pair isolation. Presence of flat wire pairs and an internal separator in a cable positions additional single wires in the cable firmly against a grounded external shield, ensuring a predetermined impedance for these signal wires. Shielded flat wire pairs and cables of low metal content extend electrical signaling to the millimeter wave regimes.
摘要翻译：新型屏蔽扁平线对和电缆实现平坦，平滑的导体，绝缘粘合在一起，提供矩形横截面和等距，平滑的表面，用于高频信号电流流动。具有导电覆盖物的扁平线对和在扁平线之间的沟槽中的对称放置的屏蔽导体使得对内信号流偏移最小化。屏蔽扁平线对放置在具有正交定向的相邻线对的电缆组件内，最小化串扰并呈现串扰共模。扁平线对的这种取向由内部分离器辅助，其可以是导电的和接地的，从而提供增强的对对对隔离。电缆线和电缆内部分离器的存在将电缆中的额外单根电线牢固地固定在接地的外部屏蔽上，确保这些信号线的预定阻抗。屏蔽扁平线对和低金属含量的电缆将电信号传输到毫米波方案。

8. 发明申请

US20070069333A1 INTEGRATED INDUCTOR STRUCTURE AND METHOD OF FABRICATION 审中-公开
标题翻译：综合电感结构与制造方法
公开(公告)号：US20070069333A1
公开(公告)日：2007-03-29
申请号：US11554567
申请日：2006-10-30
申请人： Ankur Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan Wang
发明人： Ankur Crawford , Henning Braunisch , Rajendran Nair , Gilroy Vandentop , Shan Wang
IPC分类号： H01L29/00
CPC分类号： H01L23/645 , H01F17/0033 , H01F41/046 , H01L23/49822 , H01L28/10 , H01L2224/16 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H05K1/0373 , H05K1/165 , H05K3/4644 , H05K2201/086 , H05K2201/09563 , H01L2224/0401
摘要： An inductor structure comprised of a magnetic section and a single turn solenoid The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section.
摘要翻译：由磁性部分和单匝螺线管组成的电感器结构单转螺线管包含在磁性部分的一部分内并由磁性部分限定。

9. 发明授权

US06529398B1 Ferroelectric memory and method for reading the same 失效
标题翻译：铁电存储器及其读取方法
公开(公告)号：US06529398B1
公开(公告)日：2003-03-04
申请号：US09967495
申请日：2001-09-27
申请人： Rajendran Nair , David G. Chow
发明人： Rajendran Nair , David G. Chow
IPC分类号： G11C1112
CPC分类号： G11C11/22
摘要： A ferroelectric memory device and method for reading such a device utilize capacitive coupling between a reference circuit and a sense amplifier. The amount of sneak charge canceled from a data bit line depends on the relative capacitances of a coupling capacitor and another capacitor used to integrate sneak charge from a reference bit line. The use of linear-responding components improves stability.
摘要翻译：用于读取这种器件的铁电存储器件和方法利用参考电路和读出放大器之间的电容耦合。从数据位线取消的潜行电荷量取决于耦合电容器和用于集成来自参考位线的潜行电荷的另一个电容器的相对电容。线性响应元件的使用提高了稳定性。

10. 发明申请

US20080308294A1 Swizzled twisted pair cable for simultaneous skew and crosstalk minimization 审中-公开
标题翻译：旋转双绞线用于同时扭曲和串扰最小化
公开(公告)号：US20080308294A1
公开(公告)日：2008-12-18
申请号：US11818127
申请日：2007-06-14
申请人： Rajendran Nair
发明人： Rajendran Nair
IPC分类号： H01B11/02
CPC分类号： H01B11/002
摘要： A novel varied twist-rate wire pair and cable architecture are disclosed. The invention implements variable twist rate along twisted wire pair length, providing approximately equivalent physical and electrical length values for segments of such twisted wire pair, and consequently, low delay skew, and substantially minimized inter-pair crosstalk due to reduction of twist-rate correlation along the length of a UTP cable employing the invention. Due to the elimination of the need for shielding, the invention method yields flexible, low-cost cables that may be employed for extremely high data throughput applications such as HDMI. Minimized inter-pair skew also eliminates the need for channel re-alignment at the end of long cable runs. Through these benefits, the invention twisted pair and cable facilitates continued enhancements in multi-media electronics while containing cost for high-performance interconnect.
摘要翻译：公开了一种新颖的扭曲线对和电缆结构。本发明实现了沿双绞线长度的可变扭转速率，为这种双绞线对的段提供大致相等的物理和电长度值，因此由于扭转速率相关性的降低而导致低延迟偏差和基本上最小化的对 - 串扰沿着使用本发明的UTP电缆的长度。由于消除了对屏蔽的需要，本发明方法产生可用于诸如HDMI之类的极高数据吞吐量应用的灵活的低成本电缆。最小化的对间偏斜也消除了在长电缆运行结束时对通道重新对准的需要。通过这些优点，本发明的双绞线和电缆有助于多媒体电子设备的持续增强，同时还包含高性能互连的成本。

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