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    • 2. 发明授权
    • Adaptive body biasing circuit and method
    • 自适应体偏置电路及方法
    • US06448840B2
    • 2002-09-10
    • US09452080
    • 1999-11-30
    • James T. KaoVivek K. DeSiva G. NarendraRajendran Nair
    • James T. KaoVivek K. DeSiva G. NarendraRajendran Nair
    • H03K301
    • H01L27/0222H03K17/145H03K2217/0018
    • An adaptive body bias circuit forward or reverse biases bodies of transistors within a compensated circuit as a result of measured parameters of an integrated circuit. The adaptive body bias circuit includes a matched circuit that includes a replica of a signal path within the compensated circuit. The phase of a clock signal at the input to the matched circuit is compared to a phase of a delayed clock signal at the output of the matched circuit. When the delay through the matched circuit varies about one period of the clock signal, a non-zero error value is produced. A bias voltage is generated as a function of the error value, and the bias voltage is applied to the compensated circuit as well as the matched circuit. Integrated circuits can include many adaptive body bias circuits. Bias values can be stored in memories for later use, and bias values within memories can be updated periodically to compensate the circuit over time.
    • 作为集成电路的测量参数的结果,自适应体偏置电路正向或反向偏置补偿电路内的晶体管本体。 自适应体偏置电路包括匹配电路,其包括补偿电路内的信号路径的副本。 将匹配电路的输入端的时钟信号的相位与匹配电路输出端的延迟时钟信号的相位进行比较。 当通过匹配电路的延迟在时钟信号的一个周期上变化时,产生非零误差值。 产生偏置电压作为误差值的函数,并且偏置电压被施加到补偿电路以及匹配电路。 集成电路可以包括许多自适应体偏置电路。 偏置值可以存储在存储器中以供以后使用,并且周期性地更新存储器内的偏置值以补偿电路随时间变化。
    • 3. 发明授权
    • Frequency divider and method
    • 分频器和方法
    • US06229357B1
    • 2001-05-08
    • US09388562
    • 1999-09-02
    • Rajendran NairSiva G. Narendra
    • Rajendran NairSiva G. Narendra
    • H03B1900
    • H03K3/037
    • A frequency divider includes a pulse generator, a latch with differential outputs, and switches responsive to the state of the latch. The latch changes logical state in response to signal pulses produced by the pulse generator. The signal pulses are produced by the pulse generator in response to rising edges of an input signal applied to the pulse generator. A first output alignment circuit provides additional drive strength to a first of the differential outputs when it is transitioning high. A second output alignment circuit provides additional drive strength to a second of the differential outputs when it is transitioning high.
    • 分频器包括脉冲发生器,具有差分输出的锁存器和响应于锁存器状态的开关。 锁存器响应脉冲发生器产生的信号脉冲改变逻辑状态。 响应于施加到脉冲发生器的输入信号的上升沿,由脉冲发生器产生信号脉冲。 当第一输出对准电路转变为高电平时,第一差分输出端提供额外的驱动强度。 当第二输出对准电路转变为高电平时,向第二差分输出端提供额外的驱动强度。
    • 4. 发明授权
    • Method and apparatus for weak inversion mode MOS decoupling capacitor
    • 弱反转模式MOS去耦电容器的方法和装置
    • US06849909B1
    • 2005-02-01
    • US09677698
    • 2000-09-28
    • Rajendran NairSiva G. NarendraTanay KarnikVivek K. De
    • Rajendran NairSiva G. NarendraTanay KarnikVivek K. De
    • H01L27/08H01L31/119H01L29/088H01L29/90
    • H01L27/0811Y10S257/901
    • A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.
    • 描述了用于提供弱反型模式金属氧化物半导体(MOS)去耦电容器的方法和装置。 在一个实施例中,增强型p沟道MOS(PMOS)晶体管由其功能与常用功能不同的栅极材料构成。 在一个示例性实施方案中,使用铂硅酸盐(PtSi)。 在替代实施例中,可以通过修改衬底的掺杂剂水平来改变PMOS晶体管的阈值电压。 在任一实施例中,晶体管的平带幅度偏移用于构造晶体管的材料的变化。 当这种晶体管与连接到正电源电压的栅极引线连接,而其他引线连接到负(接地)电源电压时,会产生改进的去耦电容。