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1. 发明授权

US06773986B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06773986B2
公开(公告)日：2004-08-10
申请号：US10186662
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.
摘要翻译：为了在具有存储电容器作为存储元件的半导体存储器件中实现最高可能的积分密度，根据本发明的方法以基本上垂直延伸的方式形成电容器器件，结果实现基本上三维配置和配置延伸到用于电容器器件的第三维度中，在存储电容器的生产之后形成存储电容器的接触连接。

2. 发明授权

US06704219B2 FeRAM memory and method for manufacturing it 失效
标题翻译： FeRAM存储器及其制造方法
公开(公告)号：US06704219B2
公开(公告)日：2004-03-09
申请号：US10186645
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , H01L28/86
摘要： To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.
摘要翻译：为了以特别节省空间的方式制造FeRAM存储器，因此增加存储密度，制造方法形成用作存储元件的多个电容器器件中的至少一些，其中多个单独的电容器与一个并联连接另一个。各个电容器具有不同强制电压的铁电或对称电介质区域，使得每个单独的电容器存在多个存储状态。

3. 发明授权

US06858492B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06858492B2
公开(公告)日：2005-02-22
申请号：US10186597
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L21/8242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/91
摘要： Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.
摘要翻译：电容器器件以基本上垂直延伸的方式形成，以便实现基本上三维配置或延伸到第三维度的配置。在制造电容器装置之后，进行插塞区域的接触。这种电容器器件在半导体存储器件中提供增加的集成密度。

4. 发明授权

US06818503B2 Method for fabricating a semiconductor memory device 失效
标题翻译：半导体存储器件的制造方法
公开(公告)号：US06818503B2
公开(公告)日：2004-11-16
申请号：US10186607
申请日：2002-07-01
申请人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Igor Kasko , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner , Volker Weinrich
发明人： Rainer Bruchhaus , Gerhard Enders , Walter Hartner , Igor Kasko , Matthias Krönke , Thomas Mikolajick , Nicolas Nagel , Michael Röhner , Volker Weinrich
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L28/60
摘要： A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.
摘要翻译：通过提供至少一些插塞区域来简化制造半导体存储器件的方法，这些插塞区域被提供用于接触电容器配置的存储电容器器件，使得插塞区域在每种情况下都具有在钝化区。

5. 发明申请

US20070040202A1 Semiconductor memory cell array having self-aligned recessed gate MOS transistors and method for forming the same 审中-公开
标题翻译：具有自对准凹栅MOS晶体管的半导体存储单元阵列及其形成方法
公开(公告)号：US20070040202A1
公开(公告)日：2007-02-22
申请号：US11206306
申请日：2005-08-18
申请人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
发明人： Gerhard Enders , Marc Strasser , Peter Voigt , Bjorn Fischer
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10861
摘要： In a semiconductor memory including an array of memory cells, each memory cell includes a trench capacitor, the trench capacitor including an inner electrode, an outer electrode and a dielectric layer disposed between the inner electrode and the outer electrode, and a selection transistor, the selection transistor including a first source/drain area, a second source/drain area and a channel region disposed between the first source/drain area and the second source/drain area in a recess, the trench capacitor and the selection transistor of each memory cell are disposed side by side, the first source/drain area of the selection transistor being electrically connected to the inner electrode of the trench capacitor, the recess in which the channel region of the selection transistor is formed being located self aligned between the trench capacitor of the memory cell and the trench capacitor of an adjacent memory cell.
摘要翻译：在包括存储单元阵列的半导体存储器中，每个存储单元包括沟槽电容器，所述沟槽电容器包括内电极，外电极和设置在内电极和外电极之间的电介质层，以及选择晶体管，选择晶体管，其包括第一源极/漏极区域，第二源极/漏极区域和设置在凹部中的第一源极/漏极区域和第二源极/漏极区域之间的沟道区域，每个存储器单元的沟槽电容器和选择晶体管并排配置，选择晶体管的第一源极/漏极区域电连接到沟槽电容器的内部电极，形成选择晶体管的沟道区域的凹槽位于沟槽电容器的沟槽电容器之间，存储单元和相邻存储单元的沟槽电容器。

6. 发明授权

US07081392B2 Method for fabricating a gate structure of a FET and gate structure of a FET 失效
标题翻译：用于制造FET的栅极结构和FET的栅极结构的方法
公开(公告)号：US07081392B2
公开(公告)日：2006-07-25
申请号：US10897403
申请日：2004-07-23
申请人： Gerhard Enders , Peter Voigt
发明人： Gerhard Enders , Peter Voigt
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/4966 , H01L29/66492 , H01L29/6653 , H01L29/66545 , H01L29/7833
摘要： A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.
摘要翻译：一种用于制造FET的栅极结构的方法，具有：（a）在半导体衬底上沉积和图案化牺牲层序列并露出栅极部分; （b）将沟道掺杂注入到栅极部分中; （c）在牺牲层序列的侧壁处沉积和图案化间隔物，形成未被间隔物覆盖的栅极部分; （d）将掩模材料引入未被间隔物覆盖的栅极部分; （e）相对于牺牲层序列和掩模材料选择性去除间隔物）; （f）在被去除的间隔物覆盖的区域内注入晕圈; （g）去除掩模材料; （h）在栅极部分上形成栅极; 和（j）相对于栅极选择性地去除牺牲层序列。

7. 发明授权

US07009263B2 Field-effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US07009263B2
公开(公告)日：2006-03-07
申请号：US10830675
申请日：2004-04-23
申请人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
发明人： Gerhard Enders , Bjoern Fischer , Helmut Schneider , Peter Voigt
IPC分类号： H01L29/76
CPC分类号： H01L29/0649 , H01L29/1033
摘要： A field-effect transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a channel region formed in the semiconductor substrate, wherein the source region is connected to a source terminal electrode and the drain region is connected to a drain terminal electrode, wherein the channel region comprises a first narrow width channel region and a second narrow width channel region connected in parallel regarding the source terminal electrode and the drain terminal electrode, and wherein the first narrow width channel region and/or the second narrow width channel region comprise lateral edges narrowing the width of the narrow width channel region is such a way that a channel formation in the narrow width channel region is influenced by a mutually influencing effect of the lateral edges, and a gate electrode arranged above the first and second narrow width channel regions.
摘要翻译：场效应晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，形成在半导体衬底中的沟道区域，其中源极区域连接到源极端子电极，漏极区域连接到漏极端子电极，其中沟道区域包括关于源极端子电极和漏极端子电极并联连接的第一窄宽度沟道区域和第二窄度沟道区域，并且其中第一窄宽度沟道区域和/或第二窄宽度沟道区域包括使窄宽度沟道区域的宽度变窄的横向边缘，使得窄宽度沟道区域中的沟道形成受到横向边缘的相互影响的影响，电极，布置在第一和第二窄宽度通道区域的上方。

8. 发明授权

US06503784B1 Double gated transistor 有权
标题翻译：双门控晶体管
公开(公告)号：US06503784B1
公开(公告)日：2003-01-07
申请号：US09670742
申请日：2000-09-27
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L218238
CPC分类号： H01L27/11 , H01L21/823885 , H01L27/092 , H01L27/1104 , H01L27/1203
摘要： A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：一种具有一对垂直双门控CMOS晶体管的半导体体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

9. 发明授权

US06472767B1 Static random access memory (SRAM) 有权
标题翻译：静态随机存取存储器（SRAM）
公开(公告)号：US06472767B1
公开(公告)日：2002-10-29
申请号：US09302757
申请日：1999-04-30
申请人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
发明人： Gerhard Enders , Thomas Schulz , Dietrich Widmann , Lothar Risch
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104
摘要： A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
摘要翻译：具有一对垂直双门控CMOS晶体管的半导体本体。在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。每个单元都有一个VDD CONTACT和一个VSS CONTACT。这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

10. 发明授权

US09159400B2 Semiconductor memory having staggered sense amplifiers associated with a local column decoder 有权
标题翻译：具有与本地列解码器相关联的交错读出放大器的半导体存储器
公开(公告)号：US09159400B2
公开(公告)日：2015-10-13
申请号：US13422697
申请日：2012-03-16
申请人： Richard Ferrant , Gerhard Enders , Carlos Mazure
发明人： Richard Ferrant , Gerhard Enders , Carlos Mazure
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/4097
摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.
摘要翻译：具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。这导致互连空间与位线平行。此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

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