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1. 发明公开

US20240354248A1 DATA TRANSFER USING COHERENT DOORBELL UPDATES 审中-公开
公开(公告)号：US20240354248A1
公开(公告)日：2024-10-24
申请号：US18756818
申请日：2024-06-27
申请人： Rahul Pal , Ashish Gupta , Randy Bright , Yoanna Baumgartner
发明人： Rahul Pal , Ashish Gupta , Randy Bright , Yoanna Baumgartner
IPC分类号： G06F12/0804 , G06F13/16
CPC分类号： G06F12/0804 , G06F13/1668 , G06F2213/0026
摘要： Systems or methods of the present disclosure may provide systems and techniques for efficiently transferring data between a host processing unit and connected devices using coherent doorbell register updates. For example, a method may include: receiving, via controller of host processing circuitry, an attempt to write data to a cacheable memory address from a processing unit of the host processing circuitry; transmitting, via the controller, an indication of the attempt to write to the cacheable memory address to a device; receiving, via the controller, an acknowledgment from the device that the cacheable memory address has been deallocated by the device; and writing, via the controller, the data to the cacheable memory address in response to the acknowledgement from the device.

2. 发明授权

US06546429B1 Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry 失效
标题翻译：非均匀存储器访问（NUMA）数据处理系统，其在目标处理节点处保存并重新发出响应于重试的请求
公开(公告)号：US06546429B1
公开(公告)日：2003-04-08
申请号：US09157835
申请日：1998-09-21
申请人： Yoanna Baumgartner , Anna Elman , Glen Douglas Harris
发明人： Yoanna Baumgartner , Anna Elman , Glen Douglas Harris
IPC分类号： G06F1516
CPC分类号： G06F15/17
摘要： A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node, with a node controller, that are coupled to a node interconnect. In response to receipt by the node controller of a request transaction transmitted from the local processing node, via the node interconnect, the node controller at the remote processing node issues the request transaction on the local interconnect. If the request transaction receives a retry response at the remote processing node, the node controller reissues the request transaction on the local interconnect at least once, thus giving the request transaction another opportunity to complete successfully.
摘要翻译：非均匀存储器访问（NUMA）计算机系统至少包括与节点互连耦合的具有节点控制器的本地处理节点和远程处理节点。响应于节点控制器接收到从本地处理节点发送的请求事务，经由节点互连，远程处理节点处的节点控制器在本地互连上发出请求事务。如果请求事务在远程处理节点处接收到重试响应，则节点控制器至少在本地互连上重新发出请求事务一次，从而为请求事务提供另一个成功完成的机会。

3. 发明授权

US06993470B2 Method of evaluating test cases in a simulation environment by harvesting 失效
公开(公告)号：US06993470B2
公开(公告)日：2006-01-31
申请号：US09891340
申请日：2001-06-26
申请人： Yoanna Baumgartner , Maureen T. Davis , Joseph D. Gerwels , Kirk E. Morrow
发明人： Yoanna Baumgartner , Maureen T. Davis , Joseph D. Gerwels , Kirk E. Morrow
IPC分类号： G06F17/50
CPC分类号： G01R31/318342 , G01R31/31835
摘要： The invention presents a method for selecting test cases in a test simulation of logic designs to improve speed and effectiveness of such testing. The method for selecting such test cases after such test cases are generated includes generating a test-coverage file and a harvest-goals file for the test case. The harvest-goals file contains a list of events and initial goal for each event. Harvest criteria is used to determined whether the number of hits for each event meets the initial goal. By applying the harvest criteria to the test case, it is determined whether to harvest the test case. The test case is saved and identified for harvest, if the test case is determined to be harvested. Also, the harvest-goals file is adjusted, if the test case is determined to be harvested.

4. 发明授权

US06338122B1 Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node 失效
标题翻译：推测性地将读取请求转发到远程处理节点的非均匀内存访问（NUMA）数据处理系统
公开(公告)号：US06338122B1
公开(公告)日：2002-01-08
申请号：US09211351
申请日：1998-12-15
申请人： Yoanna Baumgartner , Mark Edward Dean , Anna Elman
发明人： Yoanna Baumgartner , Mark Edward Dean , Anna Elman
IPC分类号： G06F1200
CPC分类号： G06F12/0815 , G06F12/0817 , G06F2212/507
摘要： A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.
摘要翻译：非均匀存储器访问（NUMA）计算机系统至少包括本地处理节点和每个耦合到节点互连的远程处理节点。本地处理节点包括本地互连，处理器和耦合到本地互连的系统存储器，以及插入在本地互连和节点互连之间的节点控制器。响应于从本地互连接收到读请求，节点控制器通过节点互连器向远程处理节点推测性地发送读请求。此后，响应于从远程处理节点接收到对读取请求的响应，节点控制器根据本地处理节点处的读取请求的分辨率处理响应。例如，在一个处理场景中，如果读请求在本地处理节点处接收到修改的干预一致性响应，节点控制器将丢弃从远程处理节点接收到的响应中包含的数据。

5. 发明授权

US06334177B1 Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system 失效
标题翻译：用于支持非均匀存储器访问系统内的软件分区和动态重新配置的方法和系统
公开(公告)号：US06334177B1
公开(公告)日：2001-12-25
申请号：US09216223
申请日：1998-12-18
申请人： Yoanna Baumgartner , Alvaro Eduardo Benavides , Mark Edward Dean , John Thomas Hollaway, Jr.
发明人： Yoanna Baumgartner , Alvaro Eduardo Benavides , Mark Edward Dean , John Thomas Hollaway, Jr.
IPC分类号： G06F1314
CPC分类号： G06F9/5077 , G06F12/0817 , G06F2212/2542
摘要： A method for supporting software partition and dynamic reconfiguration within a non-uniform memory access (NUMA) computer system is disclosed. A NUMA computer system includes multiple nodes coupled to an interconnect. Each of the nodes includes a NUMA bridge, a local system memory, and at least one processor having at least a local cache memory. Multiple groups of software partitions are formed within the NUMA computer system, and each of the software partitions is formed by a subset of the nodes. A destination map table is provided in a NUMA bridge of each of the nodes for keeping track of the nodes within a software partition. A command is forwarded to only the nodes within a software partition.
摘要翻译：公开了一种在非均匀存储器访问（NUMA）计算机系统内支持软件分区和动态重新配置的方法。 NUMA计算机系统包括耦合到互连的多个节点。每个节点包括NUMA桥，本地系统存储器和至少一个具有至少一个本地高速缓冲存储器的处理器。在NUMA计算机系统内形成多组软件分区，并且每个软件分区由节点的子集形成。在每个节点的NUMA桥中提供目的地地图表，用于跟踪软件分区内的节点。命令只转发到软件分区中的节点。

6. 发明授权

US07080011B2 Speech label accelerators and techniques for using same 有权
公开(公告)号：US07080011B2
公开(公告)日：2006-07-18
申请号：US09920900
申请日：2001-08-02
申请人： Yoanna Baumgartner , Gary Dale Carpenter , Brian E. D. Kingsbury , Harry Printz , Richard Siegmund
发明人： Yoanna Baumgartner , Gary Dale Carpenter , Brian E. D. Kingsbury , Harry Printz , Richard Siegmund
IPC分类号： G10L15/00
CPC分类号： G10L15/285
摘要： Speech Label Accelerators (SLAs) are provided that comprise an indirect memory, atom value memory, and adder circuitry. Optionally, the SLAs also comprise an accumulator, a load/accumulate multiplexer (mux), and a control unit. There are a variety of different configurations for the adder circuitry, and a configuration can be selected based on speed, power, and area requirements. A number of techniques are provided that allow a system having an SLA to handle more dimensions, atoms, or both than the SLA was originally designed for. A “zig-zag” method is provided that speeds processing in a system when using more dimensions than the SLA was originally designed for. Generally, the kernels used by the SLA will be Gaussian and separable, but non-Gaussian kernels and partially separable kernels may also be used by the SLA.

7. 发明授权

US6108764A Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention 失效
标题翻译：具有多个高速缓存的非均匀存储器访问（NUMA）数据处理系统同时保持最近状态下的数据，从该数据可以通过共享干预
公开(公告)号：US6108764A
公开(公告)日：2000-08-22
申请号：US213997
申请日：1998-12-17
申请人： Yoanna Baumgartner , Anna Elman
发明人： Yoanna Baumgartner , Anna Elman
IPC分类号： G06F9/52 , G06F12/08 , G06F15/16
CPC分类号： G06F12/0813
摘要： A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are coupled together. The first processing node includes a system memory and first and second processors that each have a respective associated cache hierarchy. The second processing node includes at least a third processor and a system memory. If the cache hierarchy of the first processor holds an unmodified copy of a cache line and receives a request for the cache line from the third processor, the cache hierarchy of the first processor sources the requested cache line to the third processor and retains a copy of the cache line in a Recent coherency state from which the cache hierarchy of the first processor can source the cache line in response to subsequent requests.
摘要翻译：非均匀存储器访问（NUMA）计算机系统包括耦合在一起的第一和第二处理节点。第一处理节点包括系统存储器和第一和第二处理器，每个具有相应的相关联的高速缓存层级。第二处理节点至少包括第三处理器和系统存储器。如果第一处理器的高速缓存层级保持高速缓存线的未修改的副本并且从第三处理器接收对高速缓存行的请求，则第一处理器的高速缓存层级将所请求的高速缓存行送到第三处理器，并保留最近相关性状态中的高速缓存行，第一处理器的高速缓存层级可从该高速缓存行响应于后续请求来源缓存行。

8. 发明授权

US5603057A System for initiating data transfer between input/output devices having separate address spaces in accordance with initializing information in two address packages 失效
标题翻译：用于根据两个地址包中的初始化信息在具有单独的地址空间的输入/输出设备之间启动数据传输的系统
公开(公告)号：US5603057A
公开(公告)日：1997-02-11
申请号：US560504
申请日：1995-11-17
申请人： Michael S. Allen , Yoanna Baumgartner , Michael J. Garcia , Charles R. Moore , Robert J. Reese
发明人： Michael S. Allen , Yoanna Baumgartner , Michael J. Garcia , Charles R. Moore , Robert J. Reese
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4217
摘要： A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, a transfer signal is transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device. A second address package, comprising a byte count and an address, are transmitted to the second device from the first device on the address bus. If data is to be transferred, the data is then transferred on the data bus. Finally, a reply signal may be transmitted between the first and second devices, acknowledging the success or failure of the data transfer.
摘要翻译：一种用于在数据处理系统内将数据从第一设备传送到第二设备的数据处理系统中的方法和系统。数据处理系统包括数据总线，地址总线，与存储器相关联的第一地址空间和与输入/输出设备相关联的第二地址空间。最初，在数据处理系统中传送传送信号。传送信号将传送标识为关于与输入/输出设备相关联的第二地址空间中的地址的传送。然后，第一地址包从地址总线上的第一设备发送到第二设备。第一地址包包括传送标识符，与第一设备相关联的第一标识符和与第二设备相关联的第二标识符。包括字节计数和地址的第二地址包从地址总线上的第一设备发送到第二设备。如果要传输数据，则数据在数据总线上传输。最后，可以在第一和第二设备之间传送应答信号，确认数据传输的成功或失败。

9. 发明授权

US07080269B2 Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains 失效
标题翻译：在具有多个时钟域的设计中实现省电睡眠模式的方法和装置
公开(公告)号：US07080269B2
公开(公告)日：2006-07-18
申请号：US10439040
申请日：2003-05-15
申请人： Yoanna Baumgartner , Sundeep Chadha , Richard Nicholas Iachetta, Jr. , Hien Minh Le , Kirk Edward Morrow
发明人： Yoanna Baumgartner , Sundeep Chadha , Richard Nicholas Iachetta, Jr. , Hien Minh Le , Kirk Edward Morrow
IPC分类号： G06F1/26
CPC分类号： G06F1/3228 , G06F1/12 , G06F1/324 , Y02D10/126
摘要： A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.
摘要翻译：提供了一种用于在具有包括主时钟域和次时钟域的多个时钟域的同步电路核中实现节电睡眠模式的系统和方法。主时钟域具有清醒，睡眠，打盹和醒来的状态。打盹和醒来的状态是唤醒和睡眠状态之间的瞬态状态。一个或多个次级时钟域各自具有二次唤醒和次要睡眠状态。打盹和醒来的状态被用来消除主时钟和次要时钟域之间的竞争条件。如果核心具有两个或多个次级时钟域，则辅助时钟域各自具有待处理的附加状态。睡眠挂起状态是二次唤醒和二次睡眠状态之间的暂态。一个或多个同步逻辑耦合在主时钟域和次时钟域之间。

10. 发明授权

US06275907B1 Reservation management in a non-uniform memory access (NUMA) data processing system 失效
标题翻译：非均匀内存访问（NUMA）数据处理系统中的预留管理
公开(公告)号：US06275907B1
公开(公告)日：2001-08-14
申请号：US09184395
申请日：1998-11-02
申请人： Yoanna Baumgartner , Gary Dale Carpenter , Mark Edward Dean , Anna Elman , James Stephen Fields, Jr. , David Brian Glasco
发明人： Yoanna Baumgartner , Gary Dale Carpenter , Mark Edward Dean , Anna Elman , James Stephen Fields, Jr. , David Brian Glasco
IPC分类号： G06F1208
CPC分类号： G06F12/0828 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node. In this manner, the coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved memory granule.
摘要翻译：非均匀存储器访问（NUMA）计算机系统包括耦合到节点互连的多个处理节点。多个处理节点至少包括一个远程处理节点，其包含具有相关联的高速缓存层级的处理器和家庭处理节点。家庭处理节点包括包含多个存储器颗粒的共享系统存储器和指示存储在除家庭处理节点之外的至少一个处理节点中的多个存储器颗粒中的存储器颗粒的副本的可能的相干状态的一致性目录。如果远程处理节点内的处理器对于不驻留在相关联的高速缓存层级中的多个存储器颗粒中的存储器颗粒进行预留，则相干目录将存储器颗粒与指示保留的存储器颗粒可能的相干状态相关联不排他地保存在远程处理节点。以这种方式，即使在保留处理器的高速缓存层级不保留预留的存储器颗粒的副本的情况下，也可以利用相干机制来管理处理器预留。

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