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1. 发明授权

US07418517B2 Methods and apparatus for distributing system management signals 失效
标题翻译：分配系统管理信号的方法和装置
公开(公告)号：US07418517B2
公开(公告)日：2008-08-26
申请号：US10356393
申请日：2003-01-30
申请人： Carl Zeitler , David Brian Glasco , Les Record , Richard R. Oehler , William G. Kulpa , Guru Prasadh , Rajesh Kota
发明人： Carl Zeitler , David Brian Glasco , Les Record , Richard R. Oehler , William G. Kulpa , Guru Prasadh , Rajesh Kota
IPC分类号： G06F15/173
CPC分类号： G06F1/189 , G06F1/24
摘要： Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.
摘要翻译：提供了用于改善计算机系统综合体内的系统管理信号的分布的方法和装置。提供了在盒子内和计算机系统盒之间传输的机构。本地路由表和一般路由表允许将系统管理信号精确地分配给与特定分区相关联的资源。对信号进行排序，将与一个或多个框相关联的资源置于适当的状态。可以使用专用线来实现计算机系统中的盒子之间的信号分配。

2. 发明授权

US07334089B2 Methods and apparatus for providing cache state information 有权
标题翻译：提供缓存状态信息的方法和装置
公开(公告)号：US07334089B2
公开(公告)日：2008-02-19
申请号：US10442845
申请日：2003-05-20
申请人： David Brian Glasco
发明人： David Brian Glasco
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. State information is provided to the remote data cache using various mechanisms including a coherence directory and augmented source done messages.
摘要翻译：根据本发明，提供了用于提高多处理器，多集群系统中的数据访问效率的方法和装置。允许各种事务在本地完成的机制通过提供与系统中的各种群集相关联的远程数据高速缓存来实现。远程数据高速缓存接收远程集群中存储线路的数据和状态信息。使用包括相干目录和增强源完成消息的各种机制将状态信息提供给远程数据高速缓存。

3. 发明授权

US07251698B2 Address space management in systems having multiple multi-processor clusters 有权
标题翻译：具有多个多处理器集群的系统中的地址空间管理
公开(公告)号：US07251698B2
公开(公告)日：2007-07-31
申请号：US10157409
申请日：2002-05-28
申请人： David Brian Glasco , Carl Zeitler , Rajesh Kota , Guru Prasadh , Richard R. Oehler
发明人： David Brian Glasco , Carl Zeitler , Rajesh Kota , Guru Prasadh , Richard R. Oehler
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
摘要翻译：描述了一种多处理器计算机系统，其中提供地址映射，路由和事务识别机制，其使得能够互连多个多处理器集群，其中互连的处理器的数量超过有限的地址，节点标识和交易标签与每个单独的集群相关联的空间。

4. 发明授权

US06920532B2 Cache coherence directory eviction mechanisms for modified copies of memory lines in multiprocessor systems 失效
标题翻译：多处理器系统中内存条修改副本的缓存一致性目录驱逐机制
公开(公告)号：US06920532B2
公开(公告)日：2005-07-19
申请号：US10289521
申请日：2002-11-05
申请人： David Brian Glasco , Rajesh Kota , Sridhar K. Valluru
发明人： David Brian Glasco , Rajesh Kota , Sridhar K. Valluru
IPC分类号： G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/082 , G06F12/0828 , G06F12/121
摘要： Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. The cache coherence controller is operable to initiate eviction of an entry in its directory corresponding to a modified copy of a memory line by sending a request to merge an empty data field with the modified copy of the memory line to a corresponding memory controller.
摘要翻译：描述了用于具有多个多处理器集群的计算机系统中的缓存一致性目录驱逐机制。每个集群中的高速缓存一致性控制器促成了集群之间的交互。高速缓存一致性目录与每个高速缓存一致性控制器相关联，用于识别与远程集群中缓存的本地集群相关联的存储器线。高速缓存一致性控制器可操作以通过发送将空数据字段与存储器线的修改副本合并到对应的存储器控制器的请求来启动对其对应于存储器线的修改副本的目录中的条目的驱逐。

5. 发明授权

US06269428B1 Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system 失效
标题翻译：用于避免由于在非均匀存储器访问系统内的无效事务的碰撞而产生活动锁的方法和系统
公开(公告)号：US06269428B1
公开(公告)日：2001-07-31
申请号：US09259367
申请日：1999-02-26
申请人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco
发明人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F12/0813
摘要： A method for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request by a processor of a first node to invalidate a remote copy of a cache line also stored within its cache memory at substantially the same time when a processor of a second node is also requesting to invalidate said cache line, one of the two requests is allowed to complete. The allowed request is the first request to complete without retry at the point of coherency, typically the home node. Subsequently, the other one of the two requests is permitted to complete.
摘要翻译：公开了一种用于避免由于在非均匀存储器访问系统内的无效事务的冲突而导致的活动锁定的方法。 NUMA计算机系统包括耦合到互连的至少两个节点。两个节点中的每一个包括本地系统存储器。响应于第一节点的处理器在第二节点的处理器也要求使所述高速缓存行无效的基本上同时存储在其高速缓冲存储器中的高速缓存行的远端副本的请求时，这两个请求被允许完成。允许的请求是第一个完成的请求，而不是在一致性的时候重试，通常是家庭节点。随后，两个请求中的另一个被允许完成。

6. 发明授权

US6145032A System for recirculation of communication transactions in data processing in the event of communication stall 失效
标题翻译：在通信失速的情况下数据处理中通信事务的再循环系统
公开(公告)号：US6145032A
公开(公告)日：2000-11-07
申请号：US157894
申请日：1998-09-21
申请人： John Peyton Bannister , Gary Dale Carpenter , David Brian Glasco
发明人： John Peyton Bannister , Gary Dale Carpenter , David Brian Glasco
IPC分类号： H04L12/56 , G06F3/00
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9031
摘要： A data recirculation apparatus for a data processing system includes at least one output buffer from which data are output onto an interconnect, a plurality of input storage areas from which data are selected for storage within the output buffer, and selection logic that selects data from the plurality of input storage areas for storage within the output buffer. In addition, the data recirculation apparatus includes buffer control logic that, in response to a determination that a particular datum has stalled in the output buffer, causes the particular datum to be removed from the output buffer and stored in one of the plurality of input storage areas. In one embodiment, the recirculated data has a dedicated input storage area.
摘要翻译：用于数据处理系统的数据再循环装置包括至少一个输出缓冲器，数据从该输出缓冲器输出到互连上，多个输入存储区域，数据被选择用于存储在输出缓冲器内;以及选择逻辑，其从多个输入存储区域用于存储在输出缓冲器内。此外，数据再循环装置包括缓冲器控制逻辑，其响应于确定特定数据在输出缓冲器中停滞而导致特定数据从输出缓冲器中移除并存储在多个输入存储器地区在一个实施例中，再循环数据具有专用输入存储区域。

7. 发明授权

US07577755B2 Methods and apparatus for distributing system management signals 失效
标题翻译：分配系统管理信号的方法和装置
公开(公告)号：US07577755B2
公开(公告)日：2009-08-18
申请号：US10300408
申请日：2002-11-19
申请人： Carl Zeitler , David Brian Glasco , Les Record , Richard R. Oehler , William G. Kulpa , Guru Prasadh , Rajesh Kota
发明人： Carl Zeitler , David Brian Glasco , Les Record , Richard R. Oehler , William G. Kulpa , Guru Prasadh , Rajesh Kota
IPC分类号： G06F15/16 , G06F11/00
CPC分类号： G06F1/324 , G06F1/24 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.
摘要翻译：提供了用于改善计算机系统综合体内的系统管理信号的分布的方法和装置。提供了在盒子内和计算机系统盒之间传输的机构。本地路由表和一般路由表允许将系统管理信号精确地分配给与特定分区相关联的资源。对信号进行排序，将与一个或多个框相关联的资源置于适当的状态。可以在不使用专用线的情况下实现计算机系统复合体中的盒之间的信号分配。

8. 发明授权

US06275907B1 Reservation management in a non-uniform memory access (NUMA) data processing system 失效
标题翻译：非均匀内存访问（NUMA）数据处理系统中的预留管理
公开(公告)号：US06275907B1
公开(公告)日：2001-08-14
申请号：US09184395
申请日：1998-11-02
申请人： Yoanna Baumgartner , Gary Dale Carpenter , Mark Edward Dean , Anna Elman , James Stephen Fields, Jr. , David Brian Glasco
发明人： Yoanna Baumgartner , Gary Dale Carpenter , Mark Edward Dean , Anna Elman , James Stephen Fields, Jr. , David Brian Glasco
IPC分类号： G06F1208
CPC分类号： G06F12/0828 , G06F9/3004 , G06F9/30072 , G06F9/30087
摘要： A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node. In this manner, the coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved memory granule.
摘要翻译：非均匀存储器访问（NUMA）计算机系统包括耦合到节点互连的多个处理节点。多个处理节点至少包括一个远程处理节点，其包含具有相关联的高速缓存层级的处理器和家庭处理节点。家庭处理节点包括包含多个存储器颗粒的共享系统存储器和指示存储在除家庭处理节点之外的至少一个处理节点中的多个存储器颗粒中的存储器颗粒的副本的可能的相干状态的一致性目录。如果远程处理节点内的处理器对于不驻留在相关联的高速缓存层级中的多个存储器颗粒中的存储器颗粒进行预留，则相干目录将存储器颗粒与指示保留的存储器颗粒可能的相干状态相关联不排他地保存在远程处理节点。以这种方式，即使在保留处理器的高速缓存层级不保留预留的存储器颗粒的副本的情况下，也可以利用相干机制来管理处理器预留。

9. 发明授权

US6081874A Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect 失效
标题翻译：推测在节点互连上发出请求的非均匀内存访问（NUMA）数据处理系统
公开(公告)号：US6081874A
公开(公告)日：2000-06-27
申请号：US162828
申请日：1998-09-29
申请人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco , Richard Nicholas Iachetta, Jr.
发明人： Gary Dale Carpenter , Mark Edward Dean , David Brian Glasco , Richard Nicholas Iachetta, Jr.
IPC分类号： G06F15/163 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0813
摘要： A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.
摘要翻译：非均匀存储器访问（NUMA）数据处理系统包括至少第一处理节点和第二处理节点耦合到的节点互连。第一处理节点和第二处理节点各自包括本地互连，耦合到本地互连的处理器，耦合到本地互连的系统存储器，以及插入在本地互连和节点互连之间的节点控制器。为了减少通信延迟，第一处理节点的节点控制器通过节点互连将从第一处理节点的本地互连接收的请求事务推测发送到第二处理节点。在一个实施例中，第一处理节点的节点控制器随后将状态信号发送到第二处理节点的节点控制器，以便指示如何在第二处理节点处理请求事务。

10. 发明授权

US08185602B2 Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters 有权
标题翻译：在具有多个多处理器集群的系统中使用多个协议引擎的事务处理
公开(公告)号：US08185602B2
公开(公告)日：2012-05-22
申请号：US10289492
申请日：2002-11-05
申请人： Charles Edward Watson, Jr. , Rajesh Kota , David Brian Glasco
发明人： Charles Edward Watson, Jr. , Rajesh Kota , David Brian Glasco
IPC分类号： G06F15/16
CPC分类号： G06F13/4022 , G06F12/0815 , G06F15/17337 , G06F15/80 , G06F2212/621 , H04L69/12 , H04L69/18
摘要： A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
摘要翻译：描述了一种多处理器计算机系统，其中每个处理器集群中的事务处理分布在多个协议引擎中。每个集群包括多个本地节点和通过本地点对点架构互连的互连控制器。每个集群中的互连控制器包括用于处理事务的多个协议引擎。使用与事务相关联的目的地信息在协议引擎之间分配事务。

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